Top floating-gate flash EEPROM structure

Claim 1

A Flash EEPROM with an array of top floating gate memory cells, comprising: a plurality of parallel, conductive lines formed over a silicon substrate, whereby said parallel, conductive lines are word lines and act as a control gate at said memory cells; a first insulating layer between said parallel, conductive lines and said silicon substrate, whereby said first insulating layer is a gate oxide; a first conductive structure over vertical and horizontal surfaces of said word lines at said memory cells, and extending over a portion of said silicon substrate adjacent to said word lines, whereby said first conductive structure is a floating gate; a second insulating layer between said silicon substrate and said floating gate, whereby said second insulating layer is a tunnel oxide; a third insulating layer over the surfaces of said word lines, extending between said word lines and said floating gate; source/drain regions in said silicon substrate, implanted with a conductivity-imparting dopant, under said second insulating layer but horizontally a distance from said first insulating layer; a fourth insulating layer over said memory cells, and over said silicon substrate between said memory cells; an interconnecting metallization system over said fourth insulating layer, to connect said word lines and said source/drain regions to peripheral circuits of said array; and a means to provide voltage to said word lines and said source/drain regions, wherein said providing means are used to program said memory cells by applying a voltage of between about 10 and 20 volts to said word line, a voltage of 0 volts to a drain region, and a floating voltage to a source region.