US5621338A
Expired / Lapsed
US
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High speed configuration independent programmable macrocell
Assignee: Cypress Semiconductor Corp
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Filing: 1996-01-11
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Granted: 1997-04-15
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Expires: 2016-01-11
Abstract
Abstract A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.
Inventors
- 👤 Lin-Shih Liu
- 👤 Syed B. Raza
- 👤 Hagop Nazarian
- 👤 George M. Ansel
- 👤 Stephen M. Douglass
- 👤 Jeffery S. Hunt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
158 words
A circuit comprising: a plurality of user configurable inputs for configuring said circuit; clock logic coupled to said user configurable inputs and coupled to receive a clock input, said clock logic for generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; a switching element including at least one pass gate coupled to said clock logic to receive some of said conditional clock signals and coupled to receive an input signal for said circuit, said switching element for generating a logic output, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said pass gate; and a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
Claim 2
Dependent Claim
158 words
A circuit comprising: a plurality of user configurable inputs for configuring said circuit; clock logic coupled to said user configurable inputs and coupled to receive a clock input, said clock logic for generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; a switching element including at least one pass gate coupled to said clock logic to receive some of said conditional clock signals and coupled to receive an input signal for said circuit, said switching element for generating a logic output, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said pass gate; and a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
Claim 3
Dependent Claim
16 words
The circuit as set forth in claim 1, wherein said data path circuit comprises a register.
Claim 4
Dependent Claim
17 words
The circuit as set forth in claim 1, wherein said data path circuit comprises a combinatorial circuit.
Claim 5
Dependent Claim
21 words
The circuit as set forth in claim 1, wherein said logic function implemented in said clock logic comprises a multiplexer function.
Claim 6
Dependent Claim
21 words
The circuit as set forth in claim 1, wherein said logic function implemented in said clock logic comprises a decoder function.
Claim 7
Dependent Claim
23 words
The circuit as set forth in claim 4, wherein said multiplexer function comprises multiplexing between a D-type register, T-type register and a latch.
Claim 8
Dependent Claim
32 words
The circuit as set forth in claim 1, wherein said logic function, implemented in said clock logic, comprises a polarity function for generating a true or a bar output for said circuit.
Claim 9
Dependent Claim
111 words
The circuit as set forth in claim 1, wherein: said user configurable inputs comprise a D-type register select, a T-type resister select, a latch select and a polarity select; said logic function implemented in said clock logic comprises a multiplexer function, for selecting among a D-type flip-flop, a T-type flip-flop and a latch, said logic function comprises a toggle function for implementing a T-type flip-flop, and said logic function comprises a polarity function for generating a true or a bar output for said circuit; and said data path circuit comprises a master latch, coupled to receive said logic output, and a slave latch coupling said master latch and said circuit output.
Claim 10
Dependent Claim
85 words
The circuit as set forth in claim 8, wherein said switching element comprises: a three state inverter coupled to said input signal and being controlled by said clock logic for inverting said input data in accordance with said D-type register select, said T-type resister select, and said polarity select; and a transmission gate coupled to said input signal and being controlled by said clock logic for passing said input data in accordance with said D-type register select, said T-type resister select, and said polarity select.
Claim 11
Dependent Claim
175 words
A programmable logic device (PLD) comprising: a plurality of user configurable inputs for configuring said PLD; at least one macrocell, coupled to receive said user configurable inputs, said macrocell comprising: clock logic coupled to said user configurable inputs and coupled to receive a clock input, said clock logic for generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; a switching element including at least one transmission gate coupled to said clock logic to receive some of said conditional clock signals and coupled to receive an input signal for said circuit, said switching element for generating a logic output, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said transmission gate; and a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
Claim 12
Dependent Claim
175 words
A programmable logic device (PLD) comprising: a plurality of user configurable inputs for configuring said PLD; at least one macrocell, coupled to receive said user configurable inputs, said macrocell comprising: clock logic coupled to said user configurable inputs and coupled to receive a clock input, said clock logic for generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; a switching element including at least one transmission gate coupled to said clock logic to receive some of said conditional clock signals and coupled to receive an input signal for said circuit, said switching element for generating a logic output, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said transmission gate; and a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
Claim 13
Dependent Claim
18 words
The programmable logic device as set forth in claim 10, wherein said data path circuit comprises a register.
Claim 14
Dependent Claim
19 words
The programmable logic device as set forth in claim 10, wherein said data path circuit comprises a combinatorial circuit.
Claim 15
Dependent Claim
23 words
The programmable logic device as set forth in claim 10, wherein said logic function implemented in said clock logic comprises a multiplexer function.
Claim 16
Dependent Claim
23 words
The programmable logic device as set forth in claim 10, wherein said logic function implemented in said clock logic comprises a decoder function.
Claim 17
Dependent Claim
25 words
The programmable logic device as set forth in claim 11, wherein said multiplexer function comprises multiplexing between a D-type register, T-type register and a latch.
Claim 18
Dependent Claim
34 words
The programmable logic device as set forth in claim 10, wherein said logic function, implemented in said clock logic, comprises a polarity function for generating a true or a bar output for said circuit.
Claim 19
Dependent Claim
113 words
The programmable logic device as set forth in claim 10, wherein: said user configurable inputs comprise a D-type register select, a T-type resister select, a latch select and a polarity select; said logic function implemented in said clock logic comprises a multiplexer function, for selecting among a D-type flip-flop, a T-type flip-flop and a latch, said logic function comprises a toggle function for implementing a T-type flip-flop, and said logic function comprises a polarity function for generating a true or a bar output for said circuit; and said data path circuit comprises a master latch, coupled to receive said logic output, and a slave latch coupling said master latch and said circuit output.
Claim 20
Dependent Claim
87 words
The programmable logic device as set forth in claim 17, wherein said switching element comprises: a three state inverter coupled to said input signal and being controlled by said clock logic for inverting said input data in accordance with said D-type register select, said T-type resister select, and said polarity select; and a transmission gate coupled to said input signal and being controlled by said clock logic for passing said input data in accordance with said D-type register select, said T-type resister select, and said polarity select.
Claim 21
Independent Claim
148 words
A method for configuring a circuit comprising the steps of: receiving a plurality of user configurable inputs for configuring said circuit; receiving a clock input; generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; receiving an input signal for said circuit in a switching element including at least one pass gate; receiving some of said conditional clock signals in said switching element; generating a logic output from said switching element, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said transmission gate; and providing a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
Claim 22
Independent Claim
148 words
A method for configuring a circuit comprising the steps of: receiving a plurality of user configurable inputs for configuring said circuit; receiving a clock input; generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; receiving an input signal for said circuit in a switching element including at least one pass gate; receiving some of said conditional clock signals in said switching element; generating a logic output from said switching element, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said transmission gate; and providing a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-14 | 2000-10-14 | 2001-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-14 | 2004-10-14 | 2005-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-14 | 2008-10-14 | 2009-04-15 | $7700.00 | Window Closed / Lapsed |