Signal averager for use with motor controller

Claim 2

A signal averager for use with a motor controller for determining the changing average value of a voltage signal, the averager comprising: at least two analog integrators, the integrators integrating the voltage signal during consecutive and alternating integration periods to produce a series of integrated values, each integrated value being operated on to produce an average value which is maintained for a first part of a following period during which the other integrators are integrating; a selector that samples each integrated value during the first part of the following period, each sampled value being proportional to a cumulative value of the voltage signal during the integration period the integrated value was produced; and a discharger for setting each integrated value equal to zero after the value is sampled and during the period over which the other integrators are integrating.

Claim 3

The averager as recited in claim 1 wherein, the controller provides a calibrating constant for each integrator and the averager further includes a calibrator for mathematically combining each integrated value with a calibrating constant corresponding to the integrator that produced the integrated value to provide the average value of the voltage signal during the previous integration period.

Claim 4

The averager as recited in claim 2 wherein, prior to the integrators operating on the voltage signal, the controller provides a known DC voltage to each of the integrators to produce an integrated DC value for each of the integrators and the averager includes a divider that divides the DC voltage by each integrated DC value to produce the calibrating constants.

Claim 5

The averager as recited in claim 3 wherein the calibrator mathematically combines by multiplying an integrated value by a corresponding calibrating constant.

Claim 6

The averager as recited in claim 1 wherein the at least two integrators are a first and a second integrator, the first integrator integrates the voltage signal during all primary periods to produce a primary integrated signal and the second integrator integrates the voltage signal during all secondary periods to produce a secondary integrated signal, and the primary and secondary periods alternate and are consecutive.

Claim 7

The averager as recited in claim 5 wherein each primary period includes a first and a second period and each secondary period includes a third and a fourth period and wherein the primary integrated signal is sampled during each third period, and the primary integrated signal is set to zero during each fourth period and the secondary integrated signal is sampled during each of the first periods, and the secondary integrated signal is set to zero during each of the second periods.

Claim 8

The averager as recited in claim 1 wherein the integration periods are of identical duration.

Claim 9

The averager as recited in claim 1 wherein the voltage signal is proportional to a current signal.

Claim 10

The averager as recited in claim 1 wherein the integrators include an operational amplifier receiving the voltage signal through a resistor at its inverting input and having its non-inverting input connected to ground, a double throw switch attached to the output of the operational amplifier, a first lead of the switch connected through a first capacitor to the inverting input of the operational amplifier and the second lead of the switch connected to the inverting input of the operational amplifier through a second capacitor.

Claim 11

The averager as recited in claim 9 wherein the discharger includes two switches, one switch across each capacitor, the switches open and allowing their respective capacitors to charge up during respective integration periods and closed to form a short circuit for discharging their respective capacitors.

Claim 12

The averager as recited in claim 9 wherein the selector is a double throw switch with a first lead connected to the positive plate of the first capacitor and a second lead connected to the positive plate of the second capacitor.

Claim 13

A signal averager for use with a motor controller for determining the average value of a voltage signal, the controller determining first and second calibrating constants, the averager comprising: a first analog integrator integrating the voltage signal during all primary periods to produce a primary signal for each primary period, the primary signal being proportional to a first cumulative value of the voltage signal during the preceding primary period; a second analog integrator integrating the voltage signal during all secondary periods to produce a secondary signal for each secondary period, the secondary signal being proportional to a second cumulative value of the voltage signal during the preceding secondary period, wherein the primary and secondary periods alternate and are successive; a selector that samples each primary signal during a first part of a following secondary period and samples each secondary signal during a first part of a following primary period; a discharger for setting the primary signal equal to zero during the following secondary period after the selector samples the primary signal and setting the secondary signal equal to zero during the following primary period after the selector samples the secondary signal; and a calibrator mathematically combining the primary signal with the first calibrating constant to produce a first average signal and mathematically combining the secondary signal with the second calibrating constant to produce a second average signal, each of the first and second average signals being an average value of the voltage signal.

Claim 14

A signal averager for use with a motor controller for determining the average value of a voltage signal, the controller determining first and second calibrating constants, the averager comprising: a first analog integrator integrating the voltage signal during all primary periods to produce a primary signal for each primary period, the primary signal being proportional to a first cumulative value of the voltage signal during the preceding primary period; a second analog integrator integrating the voltage signal during all secondary periods to produce a secondary signal for each secondary period, the secondary signal being proportional to a second cumulative value of the voltage signal during the preceding secondary period, wherein the primary and secondary periods alternate and are successive; a selector that samples each primary signal during a first part of a following secondary period and samples each secondary signal during a first part of a following primary period; a discharger for setting the primary signal equal to zero during the following secondary period after the selector samples the primary signal and setting the secondary signal equal to zero during the following primary period after the selector samples the secondary signal; and a calibrator mathematically combining the primary signal with the first calibrating constant to produce a first average signal and mathematically combining the secondary signal with the second calibrating constant to produce a second average signal, each of the first and second average signals being an average value of the voltage signal.

Claim 15

The averager as recited in claim 12 wherein, prior to the integrators operating, the controller provides a known DC voltage to each of the integrators to produce an integrated DC value for each of the integrators and the averager includes a divider that divides the DC voltage by each integrated DC value to produce a first calibrating constant corresponding to the first integrator and a second calibrating constant corresponding to the second integrator.

Claim 16

The averager as recited in claim 13 wherein the calibrator mathematically combines by multiplying the primary signal by the first calibrating constant and multiplying the secondary signal by the second calibrating constant.

Claim 17

The averager as recited in claim 12 wherein each primary period includes a first and a second period and each secondary period includes a third and a fourth period and wherein the primary signal is sampled during each third period, and the primary signal is set to zero during each fourth period and the secondary signal is sampled during each of the first periods, and the secondary signal is set to zero during each of the second periods.

Claim 20

The method as recited in claim 16 wherein the controller provides calibrating constants and the method further includes the step of mathematically combining each integrated value with a calibrating constant to provide the average value of the voltage signal.

Claim 21

The method as recited in claim 17, wherein the circuit includes a plurality of integrators and the method further includes the steps of supplying a known DC voltage to each integrator during an integration period, operating on the DC voltage with each integrator to produce an integrated DC value for each integrator, and dividing the DC voltage by each resulting integrated DC value to provide the calibrating constants.

Claim 22

The method as recited in claim 18 wherein the step of mathematically combining includes the step of multiplying an integrated value by a corresponding calibrating constant.

Claim 23

The method as recited in claim 16 wherein the integration periods include primary and secondary periods that are consecutive and alternating, the step of integrating the voltage signal during consecutive and alternating integration periods includes the steps of integrating the voltage signal during all primary periods to produce a primary integrated signal and integrating the voltage signal during all secondary periods to produce a secondary integrated signal, and the step of sampling includes the steps of sampling the primary and secondary integrated signals.

Claim 24

The method as recited in claim 20 wherein each primary period includes a first and a second period and each secondary period includes a third and a fourth period and wherein the primary integrated signal is sampled during each third period and is set to zero during each fourth period and the secondary integrated signal is sampled during each of the first periods and is set to zero during each of the second periods.