US5615149A
Expired / Lapsed
US
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Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming
Assignee: Renesas Electronics Corp
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Filing: 1995-04-27
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Granted: 1997-03-25
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Expires: 2015-04-27
Abstract
Abstract A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.
Inventors
- 👤 Shinichi Kobayashi
- 👤 Takeshi Nakayama
- 👤 Yoshikazu Miyawaki
- 👤 Tomoshi Futatsuya
- 👤 Yasushi Terada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:04
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C2216/00; G11C2216/12; G11C2216/14
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
98 words
A non-volatile semiconductor memory device capable of electrically programming/erasing a plurality of bytes at one time, comprising: a plurality of bit lines; a plurality of memory cells connected to said plurality of bit lines; a plurality of latch means provided corresponding to said plurality of bit lines, each latch means holding the ground voltage or a predetermined high voltage in accordance with write data; and selecting means for periodically and repetitively selecting each of said plurality of bit lines and corresponding one of the latch means, and for connecting the selected bit line to the selected latch means.
Claim 2
Dependent Claim
98 words
A non-volatile semiconductor memory device capable of electrically programming/erasing a plurality of bytes at one time, comprising: a plurality of bit lines; a plurality of memory cells connected to said plurality of bit lines; a plurality of latch means provided corresponding to said plurality of bit lines, each latch means holding the ground voltage or a predetermined high voltage in accordance with write data; and selecting means for periodically and repetitively selecting each of said plurality of bit lines and corresponding one of the latch means, and for connecting the selected bit line to the selected latch means.
Claim 3
Dependent Claim
120 words
The non-volatile semiconductor memory device according to claim 1, wherein said selecting means includes a plurality of nodes each provided in common to a first predetermined number of said plurality of bit lines and a second predetermined number of said plurality of latch means, a plurality of first transfer gate means respectively connected between each of said plurality of bit lines and corresponding one of the nodes, a plurality of second transfer gate means respectively connected between each of said plurality of latch means and corresponding one of the nodes, and counter means for periodically and repetitively selecting and turning on each of said plurality of first transfer gate means and each of said plurality of second transfer gate means.
Claim 4
Dependent Claim
38 words
The non-volatile semiconductor memory device according to claim 2, wherein said write data includes plural bits, and said first predetermined number of bit lines and said second predetermined number of latch means are equal to said plural bits.
Claim 5
Dependent Claim
58 words
The non-volatile semiconductor memory device according to claim 2, wherein said counter means repetitively turns on each of said first transfer gate means and each of said second transfer gate means so that the write voltage is supplied to each of the bit lines for a sufficient time period to write data to each of the memory cells.
Claim 6
Dependent Claim
36 words
The non-volatile semiconductor memory device according to claim 2, wherein said second predetermined number of said plurality of latch means corresponding to each of the nodes are arranged in a direction extending along the bit lines.
Claim 7
Independent Claim
65 words
A method of operating a non-volatile semiconductor memory device, comprising the steps of: holding a plurality of signals at a ground voltage or at a predetermined high voltage in accordance with a plurality of write data, and periodically and repetitively selecting each of a plurality of bit lines and coupling the selected bit line to a corresponding one of said plurality of signals being held.
Claim 8
Independent Claim
65 words
A method of operating a non-volatile semiconductor memory device, comprising the steps of: holding a plurality of signals at a ground voltage or at a predetermined high voltage in accordance with a plurality of write data, and periodically and repetitively selecting each of a plurality of bit lines and coupling the selected bit line to a corresponding one of said plurality of signals being held.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |