Microwave integrated circuit (MIC) having a reactance element formed on a groove

Claim 2

An integrated circuit comprising: (a) a semiconductor substrate; (b) at least an active element formed on a first principal surface of said substrate; (c) a groove formed on a second principal surface of said substrate up to the first principal surface thereof; and (d) an MIC capacitor having a first electrode layer formed on at least the side wall of said groove, an insulation film formed on the first electrode layer, and a second electrode layer formed on the insulation film, so that the first and second electrode layers are disposed in the groove and facing each other through the insulation film.

Claim 3

An integrated circuit as claimed in claim 1, wherein the deepest part of said groove in the vicinity of the first principal surface is V-shaped, each side wall of the V-shaped part forms an angle of θ smaller than 90 degrees with respect to the first principal surface, and the sidewall of said groove is perpendicular to the second principal surface at the opening part of said groove in the vicinity of the second principal surface.

Claim 4

An integrated circuit as claimed in claim 2, wherein the angle θ is 30 degrees.

Claim 5

An integrated circuit as claimed in claim 1, wherein: said active element is a transistor having first and second main electrode terminals and a control electrode terminal; said groove is formed under and in contact with the first main electrode terminal; and the first electrode layer is connected to the first main electrode terminal.

Claim 6

An integrated circuit comprising: (a) a semiconductor substrate; (b) at least an active element formed on a first principal surface of said substrate; (c) a groove formed on a second principal surface of said substrate up to the first principal surface thereof; and (d) a spiral coil formed on the second principal surface in the vicinity of said groove and connected to said active element through a metal layer formed on the inner wall of said groove.

Claim 7

An integrated circuit comprising: (a) a semiconductor substrate; (b) at least an active element formed on a first principal surface of said substrate; (c) a groove formed on a second principal surface of said substrate up to the first principal surface thereof; and (d) a spiral coil formed on the second principal surface in the vicinity of said groove and connected to said active element through a metal layer formed on the inner wall of said groove.

Claim 8

An integrated circuit comprising: (a) a semiconductor substrate; (b) at least an active element formed on a first principal surface of said substrate; (c) a groove formed on a second principal surface of said substrate up to the first principal surface thereof; and (d) a coil formed in said groove.

Claim 9

An integrated circuit comprising: (a) a semiconductor substrate; (b) at least an active element formed on a first principal surface of said substrate; (c) a groove formed on a second principal surface of said substrate up to the first principal surface thereof; and (d) a coil formed in said groove.

Claim 10

An integrated circuit as claimed in claim 5, wherein: said active element is a transistor having first and second main electrode terminals and a control electrode terminal; said groove is formed under and in contact with the first main electrode terminal; and the coil is connected to the first main electrode terminal.

Claim 11

An integrated circuit as claimed in claim 1, wherein said MIM capacitor is connected on the second principal surface, to a power source electrode terminal formed on the second principal surface.

Claim 12

An integrated circuit as claimed in claim 1, further comprising a ground terminal formed on the first principal surface, a ground-groove formed on the second principal surface up to the first principal surface under the ground terminal, and a wiring layer formed on the inner wall of the ground-groove, the wiring layer electrically connecting the ground terminal on the first principal surface to a ground wiring layer formed on the second principal surface.

Claim 13

An integrated circuit as claimed in claim 9, wherein the wiring layer is extended onto the second principal surface and forms an ohmic contact with said substrate through a contact hole formed on the second principal surface.

Claim 14

An integrated circuit comprising: a semiconductor substrate having first and second principal surfaces; a transistor having first and second main electrode terminals and a control electrode terminal formed on the first principal surface of said substrate; a first groove formed on the second principal surface up to the first principal surface under the first main electrode terminal; a second groove formed on the second principal surface up to the first principal surface under the second main electrode terminal; a MIM capacitor formed in at least the first groove and connected to the first main electrode terminal; and a coil formed on at least one of an inner wall of the second groove and the second principal surface around the second groove and connected to the second main electrode terminal.

Claim 15

An integrated circuit comprising: a semiconductor substrate having first and second principal surfaces; a transistor having first and second main electrode terminals and a control electrode terminal formed on the first principal surface of said substrate; a first groove formed on the second principal surface up to the first principal surface under the first main electrode terminal; a second groove formed on the second principal surface up to the first principal surface under the second main electrode terminal; a MIM capacitor formed in at least the first groove and connected to the first main electrode terminal; and a coil formed on at least one of an inner wall of the second groove and the second principal surface around the second groove and connected to the second main electrode terminal.

Claim 16

An integrated circuit comprising: (a) a semiconductor substrate; (b) a first transistor formed on the first principal surface of said substrate, having first and second main electrode regions, first and second main electrode terminals connected to the first and second main electrode regions, respectively, and a first control electrode terminal formed between the first and second main electrode regions; (c) a second transistor formed on the first principal surface of said substrate, having third and fourth main electrode regions, third and fourth main electrode terminals connected to the third and fourth main electrode regions, respectively, and a second control electrode terminal formed between the third and fourth main electrode regions; (d) a first metal wiring layer connecting the first and third main electrode terminals to each other; (e) a first groove formed on the second principal surface of said substrate up to the first main electrode terminal; (f) a second groove formed on the second principal surface of said substrate up to the second main electrode terminal; (g) a third groove formed on the second principal surface of said substrate up to the third main electrode terminal; (h) a fourth groove formed on the second principal surface of said substrate up to the fourth main electrode terminal; (i) first and second MIM capacitors formed in said first and third grooves, respectively; (j) first and second coils formed on the second principal surface around said second and fourth grooves, respectively; (k) a second metal wiring layer formed in said second groove, to connect the second main electrode terminal and said first coil to each other; and (l) a third metal wiring layer formed in said fourth groove, to connect the fourth main electrode layer and said second coil to each other.

Claim 17

An integrated circuit comprising: (a) a semiconductor substrate; (b) a first transistor formed on the first principal surface of said substrate, having first and second main electrode regions, first and second main electrode terminals connected to the first and second main electrode regions, respectively, and a first control electrode terminal formed between the first and second main electrode regions; (c) a second transistor formed on the first principal surface of said substrate, having third and fourth main electrode regions, third and fourth main electrode terminals connected to the third and fourth main electrode regions, respectively, and a second control electrode terminal formed between the third and fourth main electrode regions; (d) a first metal wiring layer connecting the first and third main electrode terminals to each other; (e) a first groove formed on the second principal surface of said substrate up to the first main electrode terminal; (f) a second groove formed on the second principal surface of said substrate up to the second main electrode terminal; (g) a third groove formed on the second principal surface of said substrate up to the third main electrode terminal; (h) a fourth groove formed on the second principal surface of said substrate up to the fourth main electrode terminal; (i) first and second MIM capacitors formed in said first and third grooves, respectively; (j) first and second coils formed on the second principal surface around said second and fourth grooves, respectively; (k) a second metal wiring layer formed in said second groove, to connect the second main electrode terminal and said first coil to each other; and (l) a third metal wiring layer formed in said fourth groove, to connect the fourth main electrode layer and said second coil to each other.

Claim 18

An integrated circuit as claimed in claim 12, wherein each of said first to fourth grooves has V-shaped part in the vicinity of the first principal surface, each side wall of the V-shaped part forms an angle of θ smaller than 90 degrees with respect to the first principal surface, and side wall of said first to fourth grooves are substantially vertical to the second principal surface in the vicinity of the second principal surface.

Claim 19

An integrated circuit as claimed in claim 12, wherein: said first MIM capacitor has a first lower electrode layer formed on at least the inner wall of said first groove, a first insulation film formed on the first lower electrode layer, and a first upper electrode layer formed on the first insulation film, so that the first lower and upper electrode layers face each other through the first insulation film; and said second MIM capacitor has a second lower electrode layer formed on at least the inner wall of said third groove, a second insulation film formed on the second lower electrode layer, and a second upper electrode layer formed on the second insulation film, so that the second lower and upper electrode layers face each other through the second insulation film.

Claim 20

An integrated circuit as claimed in claim 14, wherein: said substrate is a semi-insulating GaAs substrate; the first, second, third, and fourth main electrode regions are high-impurity-concentration regions formed in said substrate or an epitaxial layer on said substrate; the first control electrode terminal is a first metal gate electrode terminal formed on a first channel region disposed between the first and second main electrode regions; and the second control electrode terminal is a second metal gate electrode terminal formed on a second channel region disposed between the third and fourth main electrode regions.

Claim 21

An integrated circuit as claimed in claim 6, wherein the deepest part of said groove in the vicinity of the first principal surface is V-shaped, each side wall of the V-shaped part forms an angle of θ smaller than 90 degrees with respect to the first principal surface, and the sidewall of said groove is perpendicular to the second principal surface at the opening part of said groove in the vicinity of the second principal surface.

Claim 22

An integrated circuit as claimed in claim 16, wherein the angle θ is 30 degrees.

Claim 23

An integrated circuit as claimed in claim 5 or 6, wherein said spiral coil is connected, on the second principal surface, to a power source electrode terminal formed on the second principal surface.

Claim 24

An integrated circuit as claimed in claim 5 or 6, further comprising a ground terminal formed on the first principal surface, a ground-groove formed on the second principal surface up to the first principal surface under the ground terminal, and a wiring layer formed on the inner wall of the ground-groove, the wiring layer electrically connecting the ground terminal on the first principal surface to a ground wiring layer formed on the second principal surface.

Claim 25

An integrated circuit as claimed in claim 19, wherein the wiring layer is extended onto the second principal surface and forms an ohmic contact with said substrate through a contact hole formed on the second principal surface.