Methods and apparatus for performing a write/load cache protocol

Claim 2

Apparatus for implementing a Write/Load protocol in a data processing system, wherein said system includes a remote processor and remote cache memory means associated with said remote processor and coupled to a communications bus via cache controller means and a local means which is external to said remote processor and capable of sending a Write/Load instruction that includes a data item to said remote cache memory means on said communications bus, comprising: (a) means for updating said remote cache memory means in response to the appearance on said communications bus of a Write/Load instruction sent by said local means whenever the data item included with the Write/Load instruction is stored in said remote cache memory means; and (b) means for loading said data item included with said Write/Load instruction into said remote cache memory means without any involvement by said remote processor whenever said data item appearing on said communications bus is not stored in said remote cache memory means.

Claim 3

Apparatus as set forth in claim 1 wherein said means for loading is operative to store said data item into said remote cache memory means whenever the data item appearing on said communications bus is not validly stored in said remote cache memory means.

Claim 4

Apparatus as set forth in claim 1 wherein said means for loading further comprises means for creating an entry in said remote cache memory means whenever the data item appearing on said communications bus is not stored in said remote cache memory means.

Claim 5

Apparatus as set forth in claim 3 wherein said means for loading further comprises Write Load Buffer means for temporarily storing data items to be loaded into said remote cache memory means.

Claim 6

Apparatus as set forth in claim 3 wherein said means for loading is responsive to all Write/Load instructions and associated data items broadcast over said communications bus.

Claim 7

Apparatus as set forth in claim 3 wherein said means for loading is operative to selectively respond to Write/Load instructions and associated data items appearing on said communications bus, to thereby facilitate the selective loading of data items into said remote cache memory means.

Claim 8

Apparatus as set forth in claim 3 wherein said means for updating is implemented as part of said cache controller means.

Claim 9

Apparatus as set forth in claim 3 wherein said means for loading is implemented as part of said cache controller means.

Claim 10

Apparatus as set forth in claim 3 wherein said remote cache memory means includes a plurality of cache memories, each of which is controlled by a cache controller included in said cache controller means, and further wherein each cache controller includes both said means for updating and said means for loading.

Claim 11

A computer system architecture that supports the updating and loading of a variable into cache memory of a remote processor in response to a write/Load command that includes said variable being placed on a communications bus by a local means external to said remote processor, comprising: (a) at least one remote processor; (b) cache memory owned by each of said at least one remote processor; (c) a cache controller coupling both a given cache memory and the remote processor owning said given cache memory to a communications bus; (d) a communications bus; (e) means for updating said given cache memory in response to the appearance on said communications bus of a Write/Load command that includes a variable, whenever said variable is stored as a data item in said given cache memory; and (f) means for loading said variable into said given cache memory without any involvement by said remote processor owning said given cache memory in response to the appearance on said communications bus of said Write/Load command, whenever said variable is not already stored in said given cache memory.

Claim 12

A computer system architecture that supports the updating and loading of a variable into cache memory of a remote processor in response to a write/Load command that includes said variable being placed on a communications bus by a local means external to said remote processor, comprising: (a) at least one remote processor; (b) cache memory owned by each of said at least one remote processor; (c) a cache controller coupling both a given cache memory and the remote processor owning said given cache memory to a communications bus; (d) a communications bus; (e) means for updating said given cache memory in response to the appearance on said communications bus of a Write/Load command that includes a variable, whenever said variable is stored as a data item in said given cache memory; and (f) means for loading said variable into said given cache memory without any involvement by said remote processor owning said given cache memory in response to the appearance on said communications bus of said Write/Load command, whenever said variable is not already stored in said given cache memory.

Claim 13

Apparatus as set forth in claim 10 wherein said means for loading further comprises means for creating an entry in said given cache memory whenever said variable is not stored in said given cache memory.

Claim 14

Apparatus as set forth in claim 11 wherein said means for loading is responsive to all Write/Load commands and included variables broadcast over said communications bus.

Claim 15

Apparatus as set forth in claim 11 wherein said means for loading is operative to selectively respond to Write/Load commands and included variables appearing on said communications bus, to thereby facilitate selective loading of cache memory.

Claim 16

Apparatus as set forth in claim 11 wherein said means for updating is implemented utilizing said cache controller.

Claim 17

Apparatus as set forth in claim 11 wherein said means for loading is implemented utilizing said cache controller.

Claim 18

Apparatus as set forth in claim 11 wherein said cache controller includes said both said means for updating and said means for loading.

Claim 19

A bus based computer system that facilitates the updating and loading of variables in a cache memory serving a processor and coupled to a communications bus in response to Write/Load commands and a variable associated with each such command being placed on said communications bus by a remote means not served by said cache memory, comprising: (a) means, responsive to a Write/Load command appearing on said communications bus and sent by said remote means, for updating a value in said cache memory of the variable associated with said command, whenever said variable is in said cache memory, and (b) means responsive to said Write/Load command, for creating an entry in said cache memory for said variable, and for loading said variable therein, without any involvement by said processor served by said cache memory, whenever said variable is not in said cache memory.

Claim 20

A bus based computer system that facilitates the updating and loading of variables in a cache memory serving a processor and coupled to a communications bus in response to Write/Load commands and a variable associated with each such command being placed on said communications bus by a remote means not served by said cache memory, comprising: (a) means, responsive to a Write/Load command appearing on said communications bus and sent by said remote means, for updating a value in said cache memory of the variable associated with said command, whenever said variable is in said cache memory, and (b) means responsive to said Write/Load command, for creating an entry in said cache memory for said variable, and for loading said variable therein, without any involvement by said processor served by said cache memory, whenever said variable is not in said cache memory.

Claim 21

Apparatus as set forth in claim 17 wherein said means for creating and loading is operative to selectively respond to Write/Load instructions and associated variables appearing on said communications bus, to thereby facilitate selective loading of cache memory.

Claim 22

A multiprocessor computer system including a plurality of processors, each of which has a cache memory and cache controller combination associated therewith, and a communications bus for interconnecting said plurality of processors via each of their respective associated cache controllers, comprising means for enabling at least one of said plurality of processors to load data, via said communications bus, into the cache memory associated with at least one other of said plurality of processors without any involvement by said at least one other of said plurality of processors.

Claim 23

A multiprocessor computer system including a plurality of processors, each of which has a cache memory and cache controller combination associated therewith, and a communications bus for interconnecting said plurality of processors via each of their respective associated cache controllers, comprising means for enabling at least one of said plurality of processors to load data, via said communications bus, into the cache memory associated with at least one other of said plurality of processors without any involvement by said at least one other of said plurality of processors.

Claim 24

Apparatus as set forth in claim 19 wherein said at least one of said plurality of processors issues a Write/Load instruction and places said instruction on said communications bus.

Claim 25

Apparatus as set forth in claim 20 wherein said at least one other of said plurality of processors is responsive to said Write/Load instruction.

Claim 26

A multiprocessor computer system including a plurality of processors, each of which has a cache memory and cache controller combination associated therewith, and a communications bus for interconnecting said plurality of processors via each of their respective associated cache controllers, comprising means responsive to a bus command issued by a first cache controller and appearing on said communications bus, and data associated with said bus command, to enable a second cache controller to load said data into its associated cache memory without any involvement by the processor associated with said second cache controller.

Claim 27

A multiprocessor computer system including a plurality of processors, each of which has a cache memory and cache controller combination associated therewith, and a communications bus for interconnecting said plurality of processors via each of their respective associated cache controllers, comprising means responsive to a bus command issued by a first cache controller and appearing on said communications bus, and data associated with said bus command, to enable a second cache controller to load said data into its associated cache memory without any involvement by the processor associated with said second cache controller.

Claim 28

A bus based computer architecture including at least one processor, cache memory owned by a given processor, and cache controller means for interconnecting said given processor and the cache memory owned by said processor to a communications bus, comprising means for enabling at least one external entity to load data into said cache memory via said communications bus without any involvement by said given processor.

Claim 29

A bus based computer architecture including at least one processor, cache memory owned by a given processor, and cache controller means for interconnecting said given processor and the cache memory owned by said processor to a communications bus, comprising means for enabling at least one external entity to load data into said cache memory via said communications bus without any involvement by said given processor.

Claim 30

Apparatus as set forth in claim 23 wherein said means for enabling further comprises apparatus for supporting a Write/Load cache protocol.

Claim 31

Apparatus as set forth in claim 23 wherein said external entity is a prefetch mechanism.

Claim 32

Apparatus as set forth in claim 19 wherein said means for enabling is used to perform barrier synchronization between at least two of said plurality of processors in said multiprocessor computer system.

Claim 33

Apparatus as set forth in claim 19 wherein said means for enabling is utilized to maintain the coherency of data stored in the set of cache memories associated with said plurality of processors.

Claim 34

Apparatus as set forth in claim 27 further comprising Write Load Buffer means to facilitate the temporary storage of data to be loaded into cache memory.

Claim 35

Apparatus for reducing the traffic on a communications bus interconnecting a plurality of processors in a multiprocessor computer system, comprising means for supporting a Write/Load cache coherency protocol in said computer system, whereby any one of said processors can load a shared variable into caches owned by other ones of said processors without any involvement by said other ones of said processors by broadcasting a single Write/Load command that includes a value for said shared variable on said communications bus.

Claim 36

Apparatus for reducing the traffic on a communications bus interconnecting a plurality of processors in a multiprocessor computer system, comprising means for supporting a Write/Load cache coherency protocol in said computer system, whereby any one of said processors can load a shared variable into caches owned by other ones of said processors without any involvement by said other ones of said processors by broadcasting a single Write/Load command that includes a value for said shared variable on said communications bus.

Claim 37

Apparatus as set forth in claim 29 further comprising Write Load Buffer means to facilitate the temporary storage of a value for said shared variable to be loaded into cache memory utilizing said Write/Load cache coherency protocol.

Claim 38

A processor chip, for use in a bus based computer system, wherein said processor chip includes a processor, cache memory and a cache controller for coupling said processor and cache memory to a system communications bus, comprising means responsive to a bus command and data associated with said command broadcast on said system communications bus by an entity external to said chip, for updating the contents of said cache memory with said data whenever a cache entry containing a previous value of said data is stored therein, and for otherwise loading said data into said cache memory without any involvement by said processor.

Claim 39

A processor chip, for use in a bus based computer system, wherein said processor chip includes a processor, cache memory and a cache controller for coupling said processor and cache memory to a system communications bus, comprising means responsive to a bus command and data associated with said command broadcast on said system communications bus by an entity external to said chip, for updating the contents of said cache memory with said data whenever a cache entry containing a previous value of said data is stored therein, and for otherwise loading said data into said cache memory without any involvement by said processor.

Claim 40

Apparatus as set forth in claim 31 wherein said processor chip is responsive to bus commands issued by an external entity to support a prefetch mechanism.

Claim 41

Apparatus as set forth in claim 31 wherein said processor chip is responsive to bus commands issued by another processor chip, to maintain cache coherency.

Claim 42

Apparatus as set forth in claim 31 wherein said processor chip is responsive to bus commands issued by another processor chip, to perform barrier synchronization.

Claim 43

Apparatus as set forth in claim 31 wherein said processor chip is capable of being selectively responsive to one of said bus commands.

Claim 44

Apparatus as set forth in claim 31 wherein said processor chip is capable of being selectively responsive to one of said bus commands.

Claim 45

A bus based computer system comprising: (a) a communications bus; (b) at least one central processor unit (CPU), including a processor and cache memory, coupled to said communications bus; and (c) means for implementing a bus command structure that is operative to issue and respond to bus commands, and which is further operative in response to observing a Write/Load command on said communications bus, to enable data to be loaded into cache memory located in a given CPU by an entity other than the processor located in said given CPU without any involvement by said processor located in said given CPU.

Claim 46

A bus based computer system comprising: (a) a communications bus; (b) at least one central processor unit (CPU), including a processor and cache memory, coupled to said communications bus; and (c) means for implementing a bus command structure that is operative to issue and respond to bus commands, and which is further operative in response to observing a Write/Load command on said communications bus, to enable data to be loaded into cache memory located in a given CPU by an entity other than the processor located in said given CPU without any involvement by said processor located in said given CPU.

Claim 47

Apparatus as set forth in claim 37 wherein said entity is an external prefetch mechanism.

Claim 48

Apparatus as set forth in claim 37 wherein said entity is a processor located in a second CPU whenever said system includes a plurality of CPUs.

Claim 49

Apparatus as set forth in claim 37 wherein said means for implementing is a cache controller interconnecting both said processor and said cache memory to said bus.

Claim 52

A method as set forth in claim 41 wherein said step of loading further comprises the step of storing said data item into said cache memory means whenever the data item appearing on said communications bus is not validly stored in said cache memory means.

Claim 53

A method as set forth in claim 41 wherein said step of loading further comprises the step of creating an entry in said cache memory means whenever the data item appearing on said communications bus is not stored in said cache memory means.

Claim 54

A method as set forth in claim 43 wherein said step of loading further comprises the step of temporarily storing data items to be loaded into said cache memory means.

Claim 55

A method as set forth in claim 43 wherein said step of loading is performed in response to all Write/Load instructions and associated data items broadcast over said communications bus.

Claim 56

A method as set forth in claim 43 wherein said step of loading is selectively performed in response to Write/Load instructions and associated data items appearing on said communications bus.

Claim 57

A method as set forth in claim 43 wherein said step of updating is implemented utilizing said cache controller means.

Claim 58

A method as set forth in claim 43 wherein said step of loading is implemented utilizing said cache controller means.

Claim 61

A method as set forth in claim 49 wherein said step of creating and loading is selectively performed in response to Write/Load instructions and associated variables appearing on said communications bus.

Claim 68

A method as set forth in claim 53 wherein said external entity is a prefetch mechanism.

Claim 69

A method as set forth in claim 51 wherein said step of issuing is used to perform barrier synchronization between at least two of said plurality of processors in said multiprocessor computer system.

Claim 70

A method as set forth in claim 51 wherein said step of issuing is utilized to maintain the coherency of data stored in the set of cache memories associated with said plurality of processors.

Claim 75

A method as set forth in claim 58 wherein said processor chip is responsive to bus commands issued by an external entity to support a prefetch mechanism.

Claim 76

A method as set forth in claim 58 wherein said processor chip is responsive to bus commands issued by another processor chip, to maintain cache coherency and to perform barrier synchronization.

Claim 77

Apparatus for implementing a Write/Load bus command in a multiprocessor system having a multiplicity of processor subsystems and a bus interconnecting said processor subsystems, each of said processor subsystems having a cache serving a processor, said apparatus comprising: means for any one of said processor subsystems to broadcast a Write/Load command on said bus, said Write/Load command including a data item; means for each one of said processor subsystems to detect a Write/Load command broadcasted on said bus by any other one of said processor subsystems; means in each one of said processor subsystems, upon detection of a Write/Load command on said bus, for determining whether said data item included with said detected Write/Load command is stored in said cache of said processor subsystem detecting said Write/Load command; means in each one of said processor subsystems, upon determination that a data item included with a detected Write/Load command is stored in said cache of said processor subsystem detecting said Write/Load command, for replacing said data item stored in said cache of said processor subsystem detecting said Write/Load command with said data item included with said detected Write/Load command; means in each one of said processor subsystems, upon determination that a data item included with a detected Write/Load command is not stored in said cache of said processor subsystem detecting said Write/Load command, for storing said data item included with said detected Write/Load command in said cache of said processor subsystem detecting said Write/Load command without any involvement by the processor served by said cache, whereby any one of said processor subsystems can cause a data item to be validly stored in all of said caches of said multiprocessor system through use of said Write/Load bus command.

Claim 78

Apparatus for implementing a Write/Load bus command in a multiprocessor system having a multiplicity of processor subsystems and a bus interconnecting said processor subsystems, each of said processor subsystems having a cache serving a processor, said apparatus comprising: means for any one of said processor subsystems to broadcast a Write/Load command on said bus, said Write/Load command including a data item; means for each one of said processor subsystems to detect a Write/Load command broadcasted on said bus by any other one of said processor subsystems; means in each one of said processor subsystems, upon detection of a Write/Load command on said bus, for determining whether said data item included with said detected Write/Load command is stored in said cache of said processor subsystem detecting said Write/Load command; means in each one of said processor subsystems, upon determination that a data item included with a detected Write/Load command is stored in said cache of said processor subsystem detecting said Write/Load command, for replacing said data item stored in said cache of said processor subsystem detecting said Write/Load command with said data item included with said detected Write/Load command; means in each one of said processor subsystems, upon determination that a data item included with a detected Write/Load command is not stored in said cache of said processor subsystem detecting said Write/Load command, for storing said data item included with said detected Write/Load command in said cache of said processor subsystem detecting said Write/Load command without any involvement by the processor served by said cache, whereby any one of said processor subsystems can cause a data item to be validly stored in all of said caches of said multiprocessor system through use of said Write/Load bus command.