US5610927A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit control
Assignee: ARM Ltd
•
Filing: 1996-06-20
•
Granted: 1997-03-11
•
Expires: 2016-06-20
Abstract
Abstract An integrated circuit is described having a scan chain of the JTAG type in which there are provided a plurality of serially connected test cells 2. The test cells serve the additional function of operating during the normal operation of the integrated circuit to store signal values that are logically combined (compared) with signal values generated by the integrated circuit to yield control signals into for controlling the operation of the integrated circuit. This allows the storage capacity of the test cells to be utilised during normal operation when they would otherwise be idle.
Inventors
- 👤 Simon A. Segars
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:40
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/318566; G06F11/22; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
179 words
Apparatus for processing data, wherein said apparatus has a hardware test mode and a system mode of non-hardware testing operation, said apparatus comprising: (i) an integrated circuit; (ii) a plurality of serially connected test cells, each test cell being coupled to a respective point within said integrated circuit and being operable in said hardware test mode to exchange a signal value with said point, and at least one of said test cells being operable to store a predetermined constant signal value at least partially defining an exception condition during said system mode; (iii) a plurality of transmission devices for serially transferring signal values through said plurality of test cells; and (iv) a first circuit for logically combining said predetermined signal value stored within said at least one of said test cells with a signal value generated by said integrated circuit at a point coupled to said at least one of said test cells to detect said exception condition and to generate an exception signal for triggering exception processing operation of said integrated circuit while remaining in said system mode.
Claim 2
Dependent Claim
179 words
Apparatus for processing data, wherein said apparatus has a hardware test mode and a system mode of non-hardware testing operation, said apparatus comprising: (i) an integrated circuit; (ii) a plurality of serially connected test cells, each test cell being coupled to a respective point within said integrated circuit and being operable in said hardware test mode to exchange a signal value with said point, and at least one of said test cells being operable to store a predetermined constant signal value at least partially defining an exception condition during said system mode; (iii) a plurality of transmission devices for serially transferring signal values through said plurality of test cells; and (iv) a first circuit for logically combining said predetermined signal value stored within said at least one of said test cells with a signal value generated by said integrated circuit at a point coupled to said at least one of said test cells to detect said exception condition and to generate an exception signal for triggering exception processing operation of said integrated circuit while remaining in said system mode.
Claim 3
Dependent Claim
33 words
Apparatus as claimed in claim 1, wherein in said test mode said test cell is operable to apply a signal value to said point and to capture a signal value from said point.
Claim 4
Dependent Claim
13 words
Apparatus as claimed in claim 1, comprising a plurality of said first circuits.
Claim 5
Dependent Claim
24 words
Apparatus as claimed in claim 3, comprising a second circuit for combining signals from said plurality of first circuits to generate said exception signal.
Claim 6
Dependent Claim
40 words
Apparatus as claimed in claim 4, wherein each of the plurality of first circuits operates to generate a signal indicative of whether said predetermined signal value stored within said test cell equals said signal value generated by said integrated circuit.
Claim 7
Dependent Claim
51 words
Apparatus as claimed in claim 3, wherein said plurality of first circuits and corresponding test cells are coupled to points on bit lines of an address bus, said exception signal being generated when an address on said address bus matches an address stored within said test cells during said operation mode.
Claim 8
Dependent Claim
15 words
Apparatus as claimed in claim 1, wherein said integrated circuit comprises a central processing unit.
Claim 9
Independent Claim
140 words
A method of operating an integrated circuit having a plurality of serially corrected test cells, said method comprising the steps of: (i) during a test mode of operation, serially transferring signal values through said test cells and exchanging said signal values with said integrated circuit at respective points on said integrated circuit to which said test cells are coupled; and (ii) during a system mode of non-hardware-testing operation, logically combining a predetermined constant signal value at least partially defining an exception condition and stored within at least one of said test cells with a signal value generated by said integrated circuit at a point coupled to said at least one of said test cells to detect said exception condition and to generate an exception signal for triggering exception processing operation of said integrated circuit while remaining in said system mode.
Claim 10
Independent Claim
140 words
A method of operating an integrated circuit having a plurality of serially corrected test cells, said method comprising the steps of: (i) during a test mode of operation, serially transferring signal values through said test cells and exchanging said signal values with said integrated circuit at respective points on said integrated circuit to which said test cells are coupled; and (ii) during a system mode of non-hardware-testing operation, logically combining a predetermined constant signal value at least partially defining an exception condition and stored within at least one of said test cells with a signal value generated by said integrated circuit at a point coupled to said at least one of said test cells to detect said exception condition and to generate an exception signal for triggering exception processing operation of said integrated circuit while remaining in said system mode.
Claim 11
Independent Claim
135 words
An apparatus for processing data, wherein the apparatus has a hardware test mode and a system mode of non-hardware testing operation, the apparatus comprising: an integrated circuit; a test cell coupled to the integrated circuit, for exchanging a signal value with the integrated circuit in response to the apparatus being in the test mode and for storing a predetermined constant signal value at least partially defining an exception condition and in response to the apparatus being in the system mode; and a first circuit disposed within the test cell for, in response to the apparatus being in the system mode, logically combining the predetermined signal value with a signal value generated by the integrated circuit to detect said exception condition and to generate an exception signal for triggering exception processing operation of the integrated circuit.
Claim 12
Independent Claim
135 words
An apparatus for processing data, wherein the apparatus has a hardware test mode and a system mode of non-hardware testing operation, the apparatus comprising: an integrated circuit; a test cell coupled to the integrated circuit, for exchanging a signal value with the integrated circuit in response to the apparatus being in the test mode and for storing a predetermined constant signal value at least partially defining an exception condition and in response to the apparatus being in the system mode; and a first circuit disposed within the test cell for, in response to the apparatus being in the system mode, logically combining the predetermined signal value with a signal value generated by the integrated circuit to detect said exception condition and to generate an exception signal for triggering exception processing operation of the integrated circuit.
Claim 13
Dependent Claim
36 words
The apparatus of claim 9, wherein the apparatus comprises a plurality of test cells and wherein the apparatus includes a second circuit for combining signals from the plurality of test cells to generate the exception signal.
References Cited (Backward Citations)
WO1984002580A1
Cited
EP0271910A2
Cited
US4945536A
Cited
US5001713A
Cited
US5175447A
Cited
US5130988A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |