US5610869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-08-07
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Granted: 1997-03-11
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Expires: 2015-08-07
Abstract
Abstract A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.
Inventors
- 👤 Seung-Moon Yoo
- 👤 Ejaz ul Haq
- 👤 Yun-ho Choi
- 👤 Soo-In Cho
- 👤 Dae-Je Chin
- 👤 Nam-Soo Kang
- 👤 Seung-Hun Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:20
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
88 words
A semiconductor memory device comprising: power supply voltage level detecting means for detecting a plurality of predetermined levels of a power supply voltage to generate a plurality of detecting signals, each corresponding to one of said plurality of predetermined levels; oscillating means for generating frequency-controlled oscillation pulses in dependence upon the detecting signals; and refresh controlling means for adjusting a refresh period according to said frequency-controlled oscillating pulses of said oscillating means so that said refresh period is varied according to a variation of the power supply voltage.
Claim 2
Dependent Claim
88 words
A semiconductor memory device comprising: power supply voltage level detecting means for detecting a plurality of predetermined levels of a power supply voltage to generate a plurality of detecting signals, each corresponding to one of said plurality of predetermined levels; oscillating means for generating frequency-controlled oscillation pulses in dependence upon the detecting signals; and refresh controlling means for adjusting a refresh period according to said frequency-controlled oscillating pulses of said oscillating means so that said refresh period is varied according to a variation of the power supply voltage.
Claim 3
Dependent Claim
76 words
A semiconductor memory device as claimed in claim 1, wherein said oscillating means comprises: a reference oscillator for generating reference oscillation pulses in response to a substrate voltage level detecting signal; and frequency controlling means that receives the reference oscillation pulses and generates said frequency-controlled oscillation pulses in dependance upon said detecting signals; and the device further comprising a pumping circuit which inputs said frequency-controlled oscillation pulses and generates a pumping signal having a predetermined frequency.
Claim 4
Dependent Claim
153 words
A semiconductor memory device as claimed in claim 2, wherein said frequency controlling means comprises: counting means including a number of serially-connected counters for receiving said reference oscillation pulses to generate frequency-divided pulses; first NAND gate means receiving the detecting signals and the frequency-divided pulses to generate first NAND gate output signals, wherein frequency-divided pulses having a higher frequency are NANDed with one of said detecting signals corresponding to a lower voltage level of the power supply voltage and frequency-divided pulses having a lower frequency are NANDed with another of said detecting signals corresponding to a higher level of the power supply voltage; and second NAND gate means for receiving and performing a NAND operation on said first NAND gate output signals to generate said frequency-controlled oscillation pulses, the frequency of said frequency-controlled oscillation pulses varying according to which of said detecting signals are detected by said power supply voltage level detecting means.
Claim 5
Dependent Claim
35 words
A semiconductor memory device as claimed in any one of claims 1 to 3, wherein said frequency-controlled oscillation pulses have a higher frequency as the power supply voltage becomes lower, thereby shortening the refresh period.
Claim 6
Dependent Claim
88 words
A semiconductor memory device comprising: power supply voltage level detector which detects a plurality of predetermined levels of a power supply voltage to generate a plurality of detecting signals, each corresponding to one of said plurality of predetermined levels; an oscillator which generates frequency-controlled oscillation pulses in dependence upon the detecting signals; and a refresh control circuit that adjusts a refresh period according to said frequency-controlled oscillating pulses of said oscillator means so that said refresh period is varied according to a variation of the power supply voltage.
Claim 7
Dependent Claim
88 words
A semiconductor memory device comprising: power supply voltage level detector which detects a plurality of predetermined levels of a power supply voltage to generate a plurality of detecting signals, each corresponding to one of said plurality of predetermined levels; an oscillator which generates frequency-controlled oscillation pulses in dependence upon the detecting signals; and a refresh control circuit that adjusts a refresh period according to said frequency-controlled oscillating pulses of said oscillator means so that said refresh period is varied according to a variation of the power supply voltage.
Claim 8
Dependent Claim
76 words
A semiconductor memory device as claimed in claim 5, wherein said oscillator comprises: a reference oscillator for generating reference oscillation pulses in response to a substrate voltage level detecting signal; and a frequency control circuit that receives said reference oscillation pulses and generates said frequency-controlled oscillation pulses in dependance upon said detecting signals; and the device further comprising a pumping circuit, which inputs said frequency-controlled oscillation pulses and generates a pumping signal having a predetermined frequency.
Claim 9
Dependent Claim
149 words
A semiconductor memory device as claimed in claim 6, wherein said frequency control circuit comprises: a plurality of serially-connected counters for receiving said reference oscillation pulses to generate frequency-divided pulses; first NAND gate means receiving the detecting signals and the frequency-divided pulses to generate first NAND gate output signals, wherein frequency-divided pulses having a higher frequency are NANDed with one of said detecting signals corresponding to a lower voltage level of the power supply voltage and frequency-divided pulses having a lower frequency are NANDed with another of said detecting signals corresponding to a higher level of the power supply voltage; and a second NAND gate for receiving and performing a NAND operation on said first NAND gate output signals to generate said frequency-controlled oscillation pulses, the frequency of said frequency-controlled oscillation pulses varying according to which of said detecting signals are detected by said power supply voltage level detector.
Claim 10
Dependent Claim
35 words
A semiconductor memory device as claimed in any one of claims 5 to 7, wherein said frequency-controlled oscillation pulses have a higher frequency as the power supply voltage becomes lower, thereby shortening the refresh period.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |