US5610862A
Expired / Lapsed
US
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Pre-charged slave latch with parallel previous state memory
Assignee: STMicroelectronics lnc USA
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Filing: 1995-10-17
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Granted: 1997-03-11
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Expires: 2015-10-17
Abstract
Abstract According to the present invention, a method and structure for using pre-charged data path techniques in those applications where it is necessary to retain the previous state of data is presented. In the preferred embodiment, a Pre-Charged Slave Latch with Parallel Previous State Memory circuit of a burst SRAM employs a parallel memory element configuration. In conjunction with this parallel memory element configuration, three stages are disclosed to implement a pre-charged data path technique for a burst SRAM memory. First, external data is loaded into the Pre-Charged Slave Latch with Parallel Previous State Memory circuit. Next, during a burst address sequence state of the Burst SRAM, the previous address state is allowed to propagate through the address decode path of the burst SRAM. Finally, the output signal of the Pre-Charged Slave Latch with Parallel Previous State Memory is pre-charged to an inactive state in parallel with other circuit elements of the pre-charged address decode path. Thus, the advantages of pre-charged data path techniques such as increased gate fanout in the address decode path and increased memory access which results in faster speed may be enjoyed in conjunction with burst SRAM memories and other applications where it is necessary to retain a previous state of data.
Inventors
- 👤 Thomas A. Teel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:19
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/106
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
70 words
A method for retaining a previous state of data using a pre-charged data path technique, comprising the steps of: loading a input signal to a parallel memory element; allowing a previous state of the input signal to propagate through an address decode path to an output node of the parallel memory element; and pre-charging an output signal on the output node of the parallel memory element to an inactive state.
Claim 2
Independent Claim
70 words
A method for retaining a previous state of data using a pre-charged data path technique, comprising the steps of: loading a input signal to a parallel memory element; allowing a previous state of the input signal to propagate through an address decode path to an output node of the parallel memory element; and pre-charging an output signal on the output node of the parallel memory element to an inactive state.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein the input signal is an address signal.
Claim 4
Dependent Claim
200 words
The method of claim 1, wherein during the step of loading the input signal to the parallel memory element, a first clock signal equal to a first logic state controls a first pass gate of the parallel memory element, thereby allowing the input signal to propagate through the parallel memory element to the output node of the parallel memory element and to be stored in a storage element of the parallel memory element and wherein a second clock signal of the parallel memory element which controls a second pass gate of the parallel memory element is in an inactive state during the steps of loading the input signal to the parallel memory element; wherein the step of allowing the previous state of the input signal to propagate through an address decode path of the parallel memory element happens during a burst address sequence and the first clock signal is in an inactive state and the second clock signal is in an active state; and wherein the step of pre-charging the output signal of the parallel memory element to an inactive state occurs after the first clock signal or the second clock signal become inactive but before a next machine cycle.
Claim 5
Dependent Claim
18 words
The method of claim 3, wherein the storage element of the parallel memory element is a static latch.
Claim 6
Dependent Claim
50 words
The method of claim 3, wherein allowing the input signal to propagate through the parallel memory element to the output node of the parallel memory element and to be stored in a storage element of the parallel memory element makes the previous state of the input signal available and selectable.
Claim 7
Dependent Claim
54 words
The method of claim 3, wherein the first clock signal of the parallel memory element remains inactive while the second clock signal goes to a first logic state to allow a previous address state of the input signal to propagate through an address decode path to the output node of the parallel memory element.
Claim 8
Dependent Claim
22 words
The method of claim 1, wherein the parallel memory element is part of a clocked burst static random access memory (SRAM) device.
Claim 9
Dependent Claim
21 words
The method of claim 7, wherein the parallel memory element is a pre-charged slave latch with parallel previous state memory circuit.
Claim 10
Dependent Claim
41 words
The method of claim 7, wherein the step of allowing the previous state of the input signal to propagate through the address decode path of the parallel memory element happens during a burst address sequence of the clocked burst SRAM device.
Claim 11
Dependent Claim
54 words
The method of claim 9, wherein a first clock signal of the parallel memory element remains inactive while a second clock signal goes to a first logic state to allow the previous address state of the input signal to propagate through the address decode path to the output node of the parallel memory element.
Claim 12
Dependent Claim
25 words
The method of claim 10, wherein the second clock signal is an advance clock signal which advances the burst address sequence of the burst SRAM.
Claim 13
Dependent Claim
166 words
A parallel memory element structure for retaining a previous state of data, comprising: a first clock signal; a second clock signal; a input signal to a first pass gate of the parallel memory element structure, wherein the first pass gate is controlled by the first clock signal and the first pass gate passes through the input signal to an output node of the first pass gate when controlled to do so by the first clock signal; a first inverter element connected to an output node of the first pass gate; an output node, having an output signal, connected to an output terminal of the first inverter; a second pass gate controlled by the second clock signal and connected to an input terminal of the first inverter; and a third pass gate controlled by the first clock signal which stores a data state of the input signal in a storage element connected to the third pass gate when controlled to do so by the first clock signal.
Claim 14
Dependent Claim
166 words
A parallel memory element structure for retaining a previous state of data, comprising: a first clock signal; a second clock signal; a input signal to a first pass gate of the parallel memory element structure, wherein the first pass gate is controlled by the first clock signal and the first pass gate passes through the input signal to an output node of the first pass gate when controlled to do so by the first clock signal; a first inverter element connected to an output node of the first pass gate; an output node, having an output signal, connected to an output terminal of the first inverter; a second pass gate controlled by the second clock signal and connected to an input terminal of the first inverter; and a third pass gate controlled by the first clock signal which stores a data state of the input signal in a storage element connected to the third pass gate when controlled to do so by the first clock signal.
Claim 15
Dependent Claim
13 words
The structure of claim 12, wherein the input signal is an address signal.
Claim 16
Dependent Claim
18 words
The structure of claim 12, wherein the storage element of the parallel memory element is a static latch.
Claim 17
Dependent Claim
63 words
The structure of claim 12, wherein the input signal is loaded to the parallel memory element when the first clock signal is equal to a first logic state and controls the first pass gate of the parallel memory element to allow the input signal to propagate through an address decode path to the output node and to be stored in the storage element.
Claim 18
Dependent Claim
45 words
The structure of claim 15, wherein allowing the input signal to propagate to the output node of the parallel memory element and to be stored in the storage element of the parallel memory element makes the previous state of the input signal available and selectable.
Claim 19
Dependent Claim
49 words
The structure of claim 15, wherein the first clock signal remains inactive while the second clock signal goes to a first logic state to allow a previous address state of the input signal to propagate through the address decode path to the output node of the parallel memory element.
Claim 20
Dependent Claim
40 words
The structure of claim 15, wherein after the input signal is allowed to propagate through the address decode path, a previous state of the input signal is allowed to propagate through the address decode path during a burst address sequence.
Claim 21
Dependent Claim
55 words
The structure of claim 18, wherein after the previous state of the input signal is allowed to propagate through the address decode path during a burst address sequence, the output signal is pre-charged to an inactive state after the first clock signal or the second clock signal become inactive but before a next machine cycle.
Claim 22
Dependent Claim
23 words
The structure of claim 12, wherein the parallel memory element structure is part of a clocked burst static random access memory (SRAM) device.
Claim 23
Dependent Claim
22 words
The structure of claim 20, wherein the parallel memory element structure is a pre-charged slave latch with parallel previous state memory circuit.
Claim 24
Dependent Claim
39 words
The structure of claim 20, wherein the previous state of the input signal is allowed to propagate through the address decode path of the parallel memory element structure during a burst address sequence of the clocked burst SRAM device.
Claim 25
Dependent Claim
55 words
The structure of claim 22, wherein the first clock signal of the parallel memory element remains inactive while the second clock signal goes to a first logic state to allow the previous address state of the input signal to propagate through the address decode path to the output node of the parallel memory element structure.
Claim 26
Dependent Claim
26 words
The structure of claim 23, wherein the second clock input signal is an advance clock signal which advances the burst address sequence of the burst SRAM.
References Cited (Backward Citations)
US5491663A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |