US5608892A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Active cache for a microprocessor
Assignee: Ericsson AB
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Filing: 1995-06-09
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Granted: 1997-03-04
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Expires: 2015-06-09
Abstract
Abstract An active cache memory for use with microprocessors is disclosed. The cache is external to the microprocessor and forms a second level cache which is novel in that it is capable of performing transfers from external random access memory independently of the microprocessor. The cache also provides the ability to encache misaligned references and to transfer data to the microprocessor in bursts.
Inventors
- 👤 John F. Wakerly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:22
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0886; G06F12/0893; G06F12/0897; G06F12/0879
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
145 words
An active cache for use in a microprocessor based system comprising: a) memory bus means for accessing a random access memory, b) request-reception means for receiving a memory request, at least a portion of an address of said random access memory and data from a microprocessor, c) memory control means for performing read operations independent of said microprocessor on said random access memory, coupled to said memory bus means and said request-reception means, c) address decode means coupled to said request-reception means, said address decode means determining if said memory request is to enable said memory control means, d) means for enabling said memory control means if said address decode means indicates an active cache request and disabling said memory control means otherwise, and e) storage means for caching memory data of said random access memory for access by said microprocessor, wherein cacheability is enhanced.
Claim 2
Dependent Claim
145 words
An active cache for use in a microprocessor based system comprising: a) memory bus means for accessing a random access memory, b) request-reception means for receiving a memory request, at least a portion of an address of said random access memory and data from a microprocessor, c) memory control means for performing read operations independent of said microprocessor on said random access memory, coupled to said memory bus means and said request-reception means, c) address decode means coupled to said request-reception means, said address decode means determining if said memory request is to enable said memory control means, d) means for enabling said memory control means if said address decode means indicates an active cache request and disabling said memory control means otherwise, and e) storage means for caching memory data of said random access memory for access by said microprocessor, wherein cacheability is enhanced.
Claim 3
Dependent Claim
14 words
The active cache of claim 1 wherein said address is an unaligned word address.
Claim 4
Dependent Claim
20 words
The active cache of claim 1 wherein said memory control means has the ability to burst data to the microprocessor.
References Cited (Backward Citations)
US5237670A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |