Nand-type flash memory integrated-circuit card

Claim 2

A storage medium comprising: an input and output bus for commonly receiving zone address data, instruction data, address data and information data from an external source, and for outputting the information data to the external source; a plurality of flash memory components which receive data commonly supplied via the input and output bus and which discriminate between the instruction data, the address data and the information data according to an instruction latch enable signal, an address latch enable signal, a write-in enable signal and a read-out enable signal, all of which are input to each memory component, and which store, erase and output the information data according to the instruction data and address data; and a controller for enabling a corresponding one of the plurality of flash memory components according to the address data received via the input and output bus and a zone address latch enable signal.

Claim 3

The storage medium according to claim 1, wherein the controller comprises: first means for detecting the zone address data during a high-level of the zone address latch enable signal and for outputting the zone address data according to the detection; and second means for enabling one of the flash memory components corresponding to the zone address data output from the first means.

Claim 4

The storage medium according to claim 2, wherein the first means receives the zone address latch enable signal, the instruction latch enable signal, the address latch enable signal, the write-in enable signal and the read-out enable signal and supplies the instruction latch enable signal, the address latch enable signal, the write-in enable signal and the read-out enable signal to each of the flash memory components.

Claim 5

The storage medium according to claim 1, wherein said storage medium is an integrated circuit card.

Claim 6

The storage medium according to claim 4, wherein said integrated circuit card comprises external pins for the zone address latch enable signal, the instruction latch enable signal, the address latch enable signal, the write-in enable signal and the read-out enable signal and other external pins for said input and output bus.

Claim 7

A storage medium comprising: an input and output bus having first lines for commonly receiving zone address data, instruction data, address data and information data from an external source, and outputting the information data to the external source, and second lines for receiving and outputting the information data from and to the external source; first and second buffers for buffering the data of the first lines of the input and output bus; a third buffer for buffering the data of the second lines of the input and output bus; a plurality of flash memory components which receive data commonly supplied via a corresponding buffer and which discriminate between instruction data, the address data and the information data according to an instruction latch enable signal, an address latch enable signal, a write-in enable signal and a read-out enable signal, all of which are input to each flash memory component, and which store, erase and output the information data according to the instruction data and address data, the plurality of flash memory components having a first group which includes corresponding ones of the flash memory components which exchange data with the input and output bus via the second and third buffers; and a controller for enabling a corresponding one of the plurality of flash memory components according to the zone address data and the address data which are individually discriminated from the data commonly supplied via the input and output bus according to a mode control signal, a zone address latch enable signal and an address latch enable signal, and for selectively controlling one mode among a word mode for writing and reading the information data which is transmitted in parallel in units of a word having sixteen bits, a half-word mode for writing and reading the information data having only upper eight bits from the most significant bit (MSB) of data which is transmitted in parallel in units of a word, a byte mode for writing and reading the information data which is transmitted in parallel in units of a byte composed of eight bits, and a standby mode for awaiting data input and output with respect to all of the flash memory components.

Claim 8

A storage medium comprising: an input and output bus having first lines for commonly receiving zone address data, instruction data, address data and information data from an external source, and outputting the information data to the external source, and second lines for receiving and outputting the information data from and to the external source; first and second buffers for buffering the data of the first lines of the input and output bus; a third buffer for buffering the data of the second lines of the input and output bus; a plurality of flash memory components which receive data commonly supplied via a corresponding buffer and which discriminate between instruction data, the address data and the information data according to an instruction latch enable signal, an address latch enable signal, a write-in enable signal and a read-out enable signal, all of which are input to each flash memory component, and which store, erase and output the information data according to the instruction data and address data, the plurality of flash memory components having a first group which includes corresponding ones of the flash memory components which exchange data with the input and output bus via the second and third buffers; and a controller for enabling a corresponding one of the plurality of flash memory components according to the zone address data and the address data which are individually discriminated from the data commonly supplied via the input and output bus according to a mode control signal, a zone address latch enable signal and an address latch enable signal, and for selectively controlling one mode among a word mode for writing and reading the information data which is transmitted in parallel in units of a word having sixteen bits, a half-word mode for writing and reading the information data having only upper eight bits from the most significant bit (MSB) of data which is transmitted in parallel in units of a word, a byte mode for writing and reading the information data which is transmitted in parallel in units of a byte composed of eight bits, and a standby mode for awaiting data input and output with respect to all of the flash memory components.

Claim 9

The storage medium according to claim 6, wherein the controller comprises: an active zone controller for discriminating between the zone address data and the address data from the data commonly supplied via the input and output bus on the basis of the zone address latch enable signal and the address latch enable signal, and for outputting the zone address data and a group select signal for selecting a group including at least one of the flash memory component, activated on the basis of the zone address data and the address data; an OR gate which logically sums the instruction latch enable signal and the address latch enable signal supplied to all of the flash memory components, and which outputs a binary signal resulting from the logical summation; a first decoder for enabling one of the flash memory components of the first group according to the zone address data supplied from the active zone controller; a second decoder for enabling one of the flash memory components of the second group according to the zone address data supplied to the first decoder; and a data input and output controller for selectively enabling the first through third buffers and the first and second decoders on the basis of the group select signal, the binary signal and the mode control signal.

Claim 10

The storage medium according to claim 7, wherein said group select signal indicates that only the flash memory components of the second group are used.

Claim 11

The storage medium according to claim 7, wherein each of the first and second decoders is coupled to each of the flash memory components, so that one of the flash memory components belonging to the first group and one of the flash memory components belonging to the second group corresponding to the first group are both enabled with respect to a corresponding value of the zone address data.

Claim 12

The storage medium according to claim 9, wherein the data input and output controller enables the first and third buffers and the first and second decoders when the mode control signal indicates the word mode, and the binary signal has a first value representing that one of the instruction latch enable signal and the address latch enable signal is not supplied to the flash memory components, enables the first and second buffers and first and second decoders when mode control signal indicates the word mode, and the binary signal has a second value representing that one of the instruction latch enable signal and the address latch enable signal is supplied to the flash memory components, enables the third buffer and the second decoder when the mode control signal indicates the half-word mode, enables the first buffer and the first decoder when the mode control signal indicates the byte mode, and the group select signal selects the first group, enables the second buffer and the second decoder when the mode control signal indicates the byte mode, and the group select signal selects the second group, and disables the first and second decoders and the first through third buffers when the mode control signal indicates the standby mode.

Claim 13

The storage medium according to claim 6, wherein said storage medium is an integrated circuit card.

Claim 14

The storage medium according to claim 11, wherein said integrated circuit card comprises external pins for the zone address latch enable signal, the instruction latch enable signal, the address latch enable signal, the write-in enable signal and the read-out enable signal and other external pins for said input and output bus.

Claim 15

The storage medium according to claim 6, wherein the controller enables both one of the flash memory components belonging to the first group and one of the flash memory components belonging to the second group corresponding to the first group when the mode control signal indicating the word mode is applied thereto, enables one of the flash memory components belonging to the second group when the mode control signal indicating the half-word mode is applied thereto, and enables one of the NAND-type flash memory components belonging to one of the first and second groups when the mode control signal indicating the byte mode is applied thereto.