Battery back-up for electronic circuits

Claim 3

A battery back-up system for a power supply, comprising: a) a first switch leading from the power supply to a load, and a second switch leading from the battery to the load; b) a flip-flop having outputs Q and Q, each controlling a respective switch; c) a comparator for comparing power supply voltage, V POWER , with battery voltage, V BATTERY , and if V BATTERY exceeds V POWER by a predetermined amount, changing the outputs of the flip-flop such that the first switch is OFF and the second switch is ON.

Claim 4

A battery back-up system for a power supply, comprising: a) a first switch leading from the power supply to a load, and a second switch leading from the battery to the load; b) a flip-flop having outputs Q and Q, each controlling a respective switch; c) a comparator for comparing power supply voltage, V POWER , with battery voltage, V BATTERY , and if V BATTERY exceeds V POWER by a predetermined amount, changing the outputs of the flip-flop such that the first switch is OFF and the second switch is ON.

Claim 5

Apparatus according to claim 2 in which the comparator comprises a pair of p-n-p bipolar junction transistors.

Claim 6

A battery back-up system for a power supply, comprising: a) a flip-flop, having outputs Q and Q; b) a switch, M1, actuated by Q and connecting between the power supply and a terminal; c) a switch, M2, actuated by Q and connecting between the battery and the terminal; and d) means for i) causing Q to actuate M1 when the power supply voltage exceeds the battery voltage, and ii) causing Q to actuate M2 when the battery voltage exceeds the power supply voltage.

Claim 7

A battery back-up system for a power supply, comprising: a) a flip-flop, having outputs Q and Q; b) a switch, M1, actuated by Q and connecting between the power supply and a terminal; c) a switch, M2, actuated by Q and connecting between the battery and the terminal; and d) means for i) causing Q to actuate M1 when the power supply voltage exceeds the battery voltage, and ii) causing Q to actuate M2 when the battery voltage exceeds the power supply voltage.

Claim 8

A power supply for equipment, comprising: a) a primary power supply lead ("PRIMARY LEAD"); b) a back-up power supply lead ("BACK-UP LEAD"); c) a low voltage lead ("Vss LEAD"); d) first and second resistors, each having one lead connected to the Vss lead; e) a power supply lead ("Vdd LEAD") leading to the equipment; f) a first FET ("FET-1") having its channel connecting between the PRIMARY LEAD and the Vdd LEAD; h) a second FET having its channel connecting between the BACK-UP LEAD and the Vdd LEAD; i) a first PNP transistor ("Q1") having i) its base connected to the Vdd LEAD; ii) its emitter connected to the PRIMARY LEAD; and iii) its collector connected the second lead of the first resistor; j) a second PNP transistor having i) its base connected to the the Vdd lead; ii) its emitter connected to the back-up lead; and iii) its collector connected to the second lead of the second resistor; and k) an RS flip-flop, having i) its R input connected to C1; ii) its S input connected to C2; iii) its Q output connected to the gate of FET1; iv) its Q output connected to the gate of FET2, wherein FET1 connects the primary lead to the Vdd lead, until the voltage of the primary lead falls one diode drop below that of E1, at which time the flip-flop turns FET1 OFF and turns FET2 ON, thereby pulling the Vdd lead to the voltage at E1.

Claim 9

A power supply for equipment, comprising: a) a primary power supply lead ("PRIMARY LEAD"); b) a back-up power supply lead ("BACK-UP LEAD"); c) a low voltage lead ("Vss LEAD"); d) first and second resistors, each having one lead connected to the Vss lead; e) a power supply lead ("Vdd LEAD") leading to the equipment; f) a first FET ("FET-1") having its channel connecting between the PRIMARY LEAD and the Vdd LEAD; h) a second FET having its channel connecting between the BACK-UP LEAD and the Vdd LEAD; i) a first PNP transistor ("Q1") having i) its base connected to the Vdd LEAD; ii) its emitter connected to the PRIMARY LEAD; and iii) its collector connected the second lead of the first resistor; j) a second PNP transistor having i) its base connected to the the Vdd lead; ii) its emitter connected to the back-up lead; and iii) its collector connected to the second lead of the second resistor; and k) an RS flip-flop, having i) its R input connected to C1; ii) its S input connected to C2; iii) its Q output connected to the gate of FET1; iv) its Q output connected to the gate of FET2, wherein FET1 connects the primary lead to the Vdd lead, until the voltage of the primary lead falls one diode drop below that of E1, at which time the flip-flop turns FET1 OFF and turns FET2 ON, thereby pulling the Vdd lead to the voltage at E1.

Claim 10

Apparatus according to claim 4 in which the switch comprises a p-channel, enhancement-mode field-effect transistor.