Method for forming buried plug contacts on semiconductor integrated circuits

Claim 1

A method for fabricating buried metal plug structures on a semiconductor substrate for making electrical interconnections, comprising the steps of: providing a semiconductor substrate having device areas and field oxide areas and further having semiconductor devices formed in part by a patterned first polysilicon layer and device contact areas formed in and on said device areas; depositing a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate; depositing a second polysilicon layer on said first insulating layer; patterning said second polysilicon layer forming openings in said second polysilicon layer aligned over said device contact areas, and said patterned second polysilicon layer forming electrically conducting portions elsewhere on said first insulating layer; depositing a blanket second insulating layer on said patterned second polysilicon layer, and elsewhere on said first insulating layer; annealing said second insulating layer and thereby forming an essentially planar surface; anisotropically and selectively etching relative to said second polysilicon layer, contact openings in said second insulating layer through openings in a photo-resist mask, some of said contact openings aligned over and larger in width than said openings in said second polysilicon layer; and continuing said selective etching, anisotropic and selective etching said first insulating layer exposed in said second polysilicon layer openings, and thereby forming said contact openings to said device contact areas, said contact openings being self-aligned to the edge of said second polysilicon layer openings; and simultaneously etching, other contact openings in said second insulating layer to the surfaces of said patterned second polysilicon layer and also etching contact openings in areas free of said patterned second polysilicon layer in said second and first insulating layers to the surface of said substrate, said second polysilicon layer providing an etch stop layer for said selective etching; removing said photoresist mask; depositing a conformal plug metal layer on said second insulating layer and within said contact openings, and thereby filling said contact openings; and blanket etching back said plug metal layer to said second insulating layer and thereby forming metal plugs in said contact openings, the surface of said metal plugs planar with the surface of said second insulating layer; depositing a first metal layer on said second insulating layer; and patterning said first metal layer and thereby forming electrical interconnections to said substrate and said patterned second polysilicon layer by contacting said metal plugs while simultaneously providing self-aligned metal plug interconnections between said patterned second polysilicon layer and said device contact areas, and thereby completing said buried metal plug structure.

Claim 2

A method for fabricating buried metal plug structures on a semiconductor substrate for making electrical interconnections, comprising the steps of: providing a semiconductor substrate having device areas and field oxide areas and further having semiconductor devices formed in part by a patterned first polysilicon layer and device contact areas formed in and on said device areas; depositing a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate; depositing a second polysilicon layer on said first insulating layer; patterning said second polysilicon layer forming openings in said second polysilicon layer aligned over said device contact areas, and said patterned second polysilicon layer forming electrically conducting portions elsewhere on said first insulating layer; depositing a blanket second insulating layer on said patterned second polysilicon layer, and elsewhere on said first insulating layer; annealing said second insulating layer and thereby forming an essentially planar surface; anisotropically and selectively etching relative to said second polysilicon layer, contact openings in said second insulating layer through openings in a photo-resist mask, some of said contact openings aligned over and larger in width than said openings in said second polysilicon layer; and continuing said selective etching, anisotropic and selective etching said first insulating layer exposed in said second polysilicon layer openings, and thereby forming said contact openings to said device contact areas, said contact openings being self-aligned to the edge of said second polysilicon layer openings; and simultaneously etching, other contact openings in said second insulating layer to the surfaces of said patterned second polysilicon layer and also etching contact openings in areas free of said patterned second polysilicon layer in said second and first insulating layers to the surface of said substrate, said second polysilicon layer providing an etch stop layer for said selective etching; removing said photoresist mask; depositing a conformal plug metal layer on said second insulating layer and within said contact openings, and thereby filling said contact openings; and blanket etching back said plug metal layer to said second insulating layer and thereby forming metal plugs in said contact openings, the surface of said metal plugs planar with the surface of said second insulating layer; depositing a first metal layer on said second insulating layer; and patterning said first metal layer and thereby forming electrical interconnections to said substrate and said patterned second polysilicon layer by contacting said metal plugs while simultaneously providing self-aligned metal plug interconnections between said patterned second polysilicon layer and said device contact areas, and thereby completing said buried metal plug structure.

Claim 12

A method for fabricating metal plug structures on a semiconductor substrate for making electrical contacts to field effect transistors, comprising the steps of: providing a semiconductor substrate having device areas and field oxide areas and further having field effect transistor (FET) gate electrodes on said device areas and electrically conducting lines elsewhere on said substrate patterned from a first polysilicon layer, said gate electrodes having adjacent source/drains areas and further comprising the steps of; depositing a sidewall material layer on said substrate; and anisotropically etching back said sidewall material layer, and thereby forming sidewall spacers on the sidewalls of said gate electrodes; doping said source/drain areas by ion implantation and forming source/drain contact areas; depositing a blanket first insulating layer on said device areas and elsewhere on said substrate; depositing a second polysilicon layer on said first insulating layer; patterning said second polysilicon layer forming openings in said second polysilicon layer aligned over said source/drain contact areas, and forming from said second polysilicon layer electrically conducting lines on said first insulating layer; depositing a blanket second insulating layer on said patterned second polysilicon layer, and elsewhere on said first insulating layer; annealing said second insulating layer and thereby forming an essentially planar surface; anisotropically and selectively etching contact openings in said second insulating layer through openings in a photoresist mask, said contact openings aligned over and larger in width than said openings in said second polysilicon layer; and thereafter continuing said anisotropic and selective etching of said first insulating layer exposed in said second polysilicon layer openings to said source/drain contact areas, thereby forming said contact openings to said source/drain contact areas, said contact openings being self-aligned to the edge of said second polysilicon layer openings; and simultaneously, etching contact openings in said second insulating layer to the surfaces of said patterned second polysilicon layer and etching other contact openings in said second and first insulating layers to the surface of said substrate; removing said photoresist mask; depositing a conformal plug metal layer on said second insulating layer and into said contact openings, and thereby filling said contact openings; and blanket etching back said plug metal layer to said second insulating layer and thereby forming metal plugs in said contact openings; depositing a first metal layer on said second insulating layer; and patterning said first metal layer forming electrical interconnections to said substrate and said patterned second polysilicon layer while providing simultaneously self-aligned metal plug interconnections between said patterned second polysilicon layer and said source/drain contacts, and thereby completing said metal plug structure.

Claim 13

A method for fabricating metal plug structures on a semiconductor substrate for making electrical contacts to field effect transistors, comprising the steps of: providing a semiconductor substrate having device areas and field oxide areas and further having field effect transistor (FET) gate electrodes on said device areas and electrically conducting lines elsewhere on said substrate patterned from a first polysilicon layer, said gate electrodes having adjacent source/drains areas and further comprising the steps of; depositing a sidewall material layer on said substrate; and anisotropically etching back said sidewall material layer, and thereby forming sidewall spacers on the sidewalls of said gate electrodes; doping said source/drain areas by ion implantation and forming source/drain contact areas; depositing a blanket first insulating layer on said device areas and elsewhere on said substrate; depositing a second polysilicon layer on said first insulating layer; patterning said second polysilicon layer forming openings in said second polysilicon layer aligned over said source/drain contact areas, and forming from said second polysilicon layer electrically conducting lines on said first insulating layer; depositing a blanket second insulating layer on said patterned second polysilicon layer, and elsewhere on said first insulating layer; annealing said second insulating layer and thereby forming an essentially planar surface; anisotropically and selectively etching contact openings in said second insulating layer through openings in a photoresist mask, said contact openings aligned over and larger in width than said openings in said second polysilicon layer; and thereafter continuing said anisotropic and selective etching of said first insulating layer exposed in said second polysilicon layer openings to said source/drain contact areas, thereby forming said contact openings to said source/drain contact areas, said contact openings being self-aligned to the edge of said second polysilicon layer openings; and simultaneously, etching contact openings in said second insulating layer to the surfaces of said patterned second polysilicon layer and etching other contact openings in said second and first insulating layers to the surface of said substrate; removing said photoresist mask; depositing a conformal plug metal layer on said second insulating layer and into said contact openings, and thereby filling said contact openings; and blanket etching back said plug metal layer to said second insulating layer and thereby forming metal plugs in said contact openings; depositing a first metal layer on said second insulating layer; and patterning said first metal layer forming electrical interconnections to said substrate and said patterned second polysilicon layer while providing simultaneously self-aligned metal plug interconnections between said patterned second polysilicon layer and said source/drain contacts, and thereby completing said metal plug structure.