US5606559A
Expired / Lapsed
US
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System and method for an efficient ATM adapter/device driver interface
Assignee: International Business Machines Corp
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Filing: 1995-08-11
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Granted: 1997-02-25
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Expires: 2015-08-11
Abstract
Abstract An ATM communications network includes a system processor having a device driver and a memory coupled to an adapter at an interface. Frames stored in the memory are transmitted to the network using a transmit ready queue residing in the adapter and defined by transmit control registers. The frames are linked together by descriptors and pointers to received ready lists maintained by the device driver. A transmit frame complete list is established in the system memory using the transmit control registers. An interrupt is generated by the adapter indicating when frame transmission is complete. Simultaneously, cells are received from the network and stored in system memory according to a free buffer list established by the device driver. A pointer is maintained by the device driver to the last entry of the receive free buffer list. The adapter maintains a pointer to the next buffer to be used from the receive free buffer list. A receive ready list is established by the device driver in system memory with the location indicated to the adapter via the receive control registers in the adapter. The receive data cells are reassembled into frames in buffers from the free buffer list. At completion of a received frame, the frame is added to an appropriate receive ready list. An interrupt is generated to the processor by the adapter when one or more completed frames reside on the receive ready list for transmission to the network.
Inventors
- 👤 Ryan L. Badger
- 👤 Kenneth J. Barker
- 👤 Paul H. Nichols
- 👤 Russell E. Schroter
- 👤 John K. Stacy
- 👤 Mark C. Wartski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:32
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L2012/5614; H04L2012/5615; H04L2012/5616; H04L2012/5638; H04L2012/5646; H04L2012/5652; H04L2012/5678; H04L2012/5681
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
131 words
In an ATM communications network, a system processor including a device driver, a system memory and an adaptor coupled together at an interface for increased system processing performance and memory utilization, comprising: a) adapter processor and control memory means included in the adapter, b) means for establishing transmit and receive control registers in the control memory; c) means for receiving data cells from the network for storage as frames on received ready lists in system memory; d) means for establishing a transmit ready queue (TRQ) in the control memory; the TRQ identifying frames for transmission on a received ready list; e) means for establishing in system memory a transmit complete list (TCL); and f) means for generating an interrupt to the device driver indicating frame transmission complete and updating the TCL.
Claim 2
Dependent Claim
131 words
In an ATM communications network, a system processor including a device driver, a system memory and an adaptor coupled together at an interface for increased system processing performance and memory utilization, comprising: a) adapter processor and control memory means included in the adapter, b) means for establishing transmit and receive control registers in the control memory; c) means for receiving data cells from the network for storage as frames on received ready lists in system memory; d) means for establishing a transmit ready queue (TRQ) in the control memory; the TRQ identifying frames for transmission on a received ready list; e) means for establishing in system memory a transmit complete list (TCL); and f) means for generating an interrupt to the device driver indicating frame transmission complete and updating the TCL.
Claim 3
Dependent Claim
56 words
The communication network of claim 1 further comprising: a) means for establishing a receive free buffer list for identifying receive buffers in system memory for storing data cells received from the network; b) means for locating the beginning of the receive free buffer lists; and c) means for indicating the end of the free buffer lists.
Claim 4
Dependent Claim
20 words
The communication network of claim 2 further comprising: means for establishing receive ready lists including buffer descriptors for completed frames.
Claim 5
Dependent Claim
30 words
The communication network of claim 3 further comprising: means for generating an interrupt to the device driver indicating that one or more completed frames resides on the received ready lists.
Claim 6
Dependent Claim
34 words
The communication network of claim 4 wherein the transmit ready queue is defined in the control memory by a base register having a top address; bottom address; a write pointer and a read pointer.
Claim 7
Dependent Claim
41 words
The communication network of claim 5 wherein the adapter processor includes a transmit sub-processor and receive sub-processor, the transmit sub-processor retrieving data from the system memory for transmission to the network and the receive sub-processor transferring data to the system memory.
Claim 8
Dependent Claim
26 words
The communication network of claim 6 further including a start of free buffer list register and a plurality of receive control registers in the control memory.
Claim 9
Dependent Claim
24 words
The communication network of claim 7 further including a receive free buffer list and end of free buffer list pointers located in system memory.
Claim 10
Dependent Claim
27 words
The communication network of claim 8 wherein system memory includes transmit frame descriptors identifying buffer locations in system memory for frames ready for transmission to the network.
Claim 11
Dependent Claim
17 words
The communication network of claim 9 wherein system memory includes receive buffer descriptors for receive buffer location.
Claim 12
Dependent Claim
25 words
The communication network of claim 10 further including a logical channel number table in control memory for relating frame addresses and descriptors to TRQ entries.
Claim 13
Dependent Claim
24 words
The communication network of claim 9 wherein the transmit ready queue contain entries of frames stored in system memory for transfer to the network.
Claim 14
Dependent Claim
36 words
The communication network of claim 10 further including a system interrupt status register in the a control memory which initiates an interrupt to the processor when a receive ready list bit is set in the register.
Claim 15
Dependent Claim
201 words
In an ATM communications network, a system processor including a device driver, a system memory and an adaptor coupled together at an interface for increased system processing performance and memory utilization, a method for increasing system processing performance and memory utilization, comprising the steps of: a) initializing transmit control registers in the adapter; b) establishing a transmit ready queue (TRQ) defined by the transmit control registers; (c) writing a transmit complete last free descriptor address indicating the end of a transmit complete list in system memory; (d) setting a TRQ write pointer to equal a TRQ read pointer indicating an empty queue in the TRQ; e) determining when a frame is ready for transmission in system memory; a "no" condition continuing the monitoring by the system processor for a frame ready for transmission; a "yes" condition indicating a frame ready to be transmitted; f) determining if the TRQ is full; g) sending a transmit request to the TRQ; h) incrementing the TRQ write pointer while the adapter monitors the TRQ to determine when the transmit write pointer equals the transmit read pointer; i) obtaining a ready frame from the system memory; and j) transmitting the ready frame to the communications network.
Claim 16
Dependent Claim
201 words
In an ATM communications network, a system processor including a device driver, a system memory and an adaptor coupled together at an interface for increased system processing performance and memory utilization, a method for increasing system processing performance and memory utilization, comprising the steps of: a) initializing transmit control registers in the adapter; b) establishing a transmit ready queue (TRQ) defined by the transmit control registers; (c) writing a transmit complete last free descriptor address indicating the end of a transmit complete list in system memory; (d) setting a TRQ write pointer to equal a TRQ read pointer indicating an empty queue in the TRQ; e) determining when a frame is ready for transmission in system memory; a "no" condition continuing the monitoring by the system processor for a frame ready for transmission; a "yes" condition indicating a frame ready to be transmitted; f) determining if the TRQ is full; g) sending a transmit request to the TRQ; h) incrementing the TRQ write pointer while the adapter monitors the TRQ to determine when the transmit write pointer equals the transmit read pointer; i) obtaining a ready frame from the system memory; and j) transmitting the ready frame to the communications network.
Claim 17
Dependent Claim
88 words
The method of claim 14 further comprising the steps of: placing the address of a just transmitted frame descriptor into the forward pointer of the descriptor pointed to by the transmit complete list pointer last free descriptor address (TCL-LFDA) register; b) linking the descriptors to the transmit complete list; c) updating a transmit complete list-last free descriptor address register with the address of the just transmitted descriptor address; and d) incrementing the transmit ready queue read pointer to initiate the next frame transmission sequence to the communication network.
Claim 18
Dependent Claim
252 words
In an ATM communications network, a system processor including a device driver, a system memory and an adaptor coupled together at an interface for increased system processing performance and memory utilization, a method for increasing system processing performance and memory utilization, comprising the steps of: a) building a linked list of descriptors for free buffers in system memory, each buffer descriptor chained to the next via a forward pointer; b) maintaining a pointer to the end of the list in the system processor; c) writing the address of the first buffer descriptor to start a free list register (SRFL) in the adapter; d) receiving an ATM cell from the network; e) determining if the cell is the first of a frame or whether a current system buffer is full; a "no" condition placing the cell into a system buffer; a "yes" condition using the address in the SRFL to locate the address of the next free buffer in the system memory; f) determining if the buffer is the last on the free buffer list; a "yes" condition notifying the system processor and discarding the cell; a "no" condition updating the SRFL with the pointer from the just obtained buffer; g) determining if the received cell is the first cell; if not, updating the forward pointer of the just completed descriptor with the system memory address of the just obtained descriptor and placing the cell into the buffer defined by the descriptor; and h) repeating steps (a-g) until the last cell is identified.
Claim 19
Dependent Claim
252 words
In an ATM communications network, a system processor including a device driver, a system memory and an adaptor coupled together at an interface for increased system processing performance and memory utilization, a method for increasing system processing performance and memory utilization, comprising the steps of: a) building a linked list of descriptors for free buffers in system memory, each buffer descriptor chained to the next via a forward pointer; b) maintaining a pointer to the end of the list in the system processor; c) writing the address of the first buffer descriptor to start a free list register (SRFL) in the adapter; d) receiving an ATM cell from the network; e) determining if the cell is the first of a frame or whether a current system buffer is full; a "no" condition placing the cell into a system buffer; a "yes" condition using the address in the SRFL to locate the address of the next free buffer in the system memory; f) determining if the buffer is the last on the free buffer list; a "yes" condition notifying the system processor and discarding the cell; a "no" condition updating the SRFL with the pointer from the just obtained buffer; g) determining if the received cell is the first cell; if not, updating the forward pointer of the just completed descriptor with the system memory address of the just obtained descriptor and placing the cell into the buffer defined by the descriptor; and h) repeating steps (a-g) until the last cell is identified.
Claim 20
Dependent Claim
102 words
The method of claim 16 further comprising the steps of: a) accessing a control memory in the adapter for the received ready list associated with a logical channel related to the cell; b) updating the descriptor pointed to by the contents of the received ready list register to point to the first descriptor of the current received frame; c) linking the just received frame to the received ready list; d) updating the received ready list to point to the last buffer descriptor for the just received frame; and e) returning to step a) for processing the next cell received from the network.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |