US5604368A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned double-gate MOSFET by selective lateral epitaxy
Assignee: International Business Machines Corp
•
Filing: 1995-03-21
•
Granted: 1997-02-18
•
Expires: 2015-03-21
Abstract
Abstract A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.
Inventors
- 👤 Yuan Taur
- 👤 Hon-Sum P. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
144 words
A double-gate MOSFET comprising: a semiconductor substrate having an upper surface, a silicon dioxide layer on said upper surface, said silicon dioxide layer having an opening therein, an epitaxial semiconductor structure formed from said opening, said semiconductor structure having a channel region between a drain region and source region, the source region, the drain region and the channel region each having a thickness, the thickness of the source region and the thickness of the drain region each being greater than the thickness of the channel region, first and second oxide layers of about 100 Å or less in thickness on first and second juxtaposed major surfaces of the channel region, said channel region having top and bottom gate electrodes formed on said first and second oxide layers, wherein said top and bottom gate electrodes are self-aligned to each other and to said channel region.
Claim 2
Dependent Claim
144 words
A double-gate MOSFET comprising: a semiconductor substrate having an upper surface, a silicon dioxide layer on said upper surface, said silicon dioxide layer having an opening therein, an epitaxial semiconductor structure formed from said opening, said semiconductor structure having a channel region between a drain region and source region, the source region, the drain region and the channel region each having a thickness, the thickness of the source region and the thickness of the drain region each being greater than the thickness of the channel region, first and second oxide layers of about 100 Å or less in thickness on first and second juxtaposed major surfaces of the channel region, said channel region having top and bottom gate electrodes formed on said first and second oxide layers, wherein said top and bottom gate electrodes are self-aligned to each other and to said channel region.
Claim 3
Dependent Claim
29 words
The double-gate MOSFET of claim 1, wherein said first and second juxtaposed major surfaces of said channel region are substantially parallel with the upper surface of said semiconductor substrate.
Claim 4
Dependent Claim
22 words
The double-gate MOSFET of claim 1, wherein said semiconductor substrate is selected from the group consisting of silicon, germanium and alloys thereof.
Claim 5
Dependent Claim
12 words
The double-gate MOSFET of claim 1, wherein said channel region is undoped.
Claim 6
Dependent Claim
34 words
The double-gate MOSFET of claim 4, wherein said substrate is doped P type and said source region is doped n type, whereby a pn junction is formed between said substrate and said source region.
Claim 7
Dependent Claim
24 words
The double-gate MOSFET of claim 1, wherein said channel region is formed by selective epitaxial growth in an empty region between two dielectric regions.
Claim 8
Dependent Claim
16 words
The double-gate MOSFET of claim 1, wherein the channel region is constructed of single crystal silicon.
References Cited (Backward Citations)
US5315143A
Cited
US5461250A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-18 | 2000-08-19 | 2001-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-18 | 2004-08-19 | 2005-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-18 | 2008-08-19 | 2009-02-18 | $7700.00 | Window Closed / Lapsed |