US5604138A
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Process for making a semiconductor MOS transistor
Assignee: SK Hynix Inc
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Filing: 1994-12-15
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Granted: 1997-02-18
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Expires: 2014-12-15
Abstract
Abstract A process for forming an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer on the second insulating layer; forming an etch inhibiting layer pattern for forming an over-sized gate on a relevant area of the second insulating layer; removing the second and third insulating layers and the conductive layer excluding the portions protected from the etch inhibiting layer, so as to form a stacked pattern consisting of the residual second insulating layer/the third insulating layer/the conductive layer; forming a first impurity ion buried layer on a relevant portion of the semiconductor substrate utilizing the stacked pattern for formation of a source/drain region; removing the etch inhibiting layer; removing an edge portion of the remaining second insulating layer of the stacked pattern for forming the final gate; removing the residual third insulating layer of the stacked pattern; etching the residual conductive layer by using the partly removed second insulating layer as the mask to form the final gate; forming a second impurity ion buried layer on the relevant portion of the semiconductor substrate for forming the LDD structure; forming a fourth insulating layer on the whole surface of the wafer; and activating the first and second ion buried layers.
Inventors
- 👤 Chang-Jae Lee
- 👤 Young-Jin Song
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:44
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
164 words
A process for forming a MOSFET having an LDD structure, comprising the steps of: (1) forming a first insulating layer on a semiconductor substrate; (2) forming a conductive layer on the first insulating layer; (3) forming a second insulating layer on the conductive layer; (4) forming a third insulating layer on the second insulating layer; (5) selectively removing portions of the third insulating layer, the second insulating layer and the conductive layer to form a stacked over-sized gate pattern; (6) forming a first impurity region in the semiconductor substrate utilizing the stacked over-sized gate pattern as a mask; (7) selectively removing an edge portion of the second insulating layer with a wet etch from the stacked over-sized gate pattern to form an undercut with respect to the third insulating layer; (8) removing the third insulating layer; (9) etching the conductive layer using the second insulating layer as a mask to form a gate; and (10) forming a second impurity region in the semiconductor substrate.
Claim 2
Dependent Claim
164 words
A process for forming a MOSFET having an LDD structure, comprising the steps of: (1) forming a first insulating layer on a semiconductor substrate; (2) forming a conductive layer on the first insulating layer; (3) forming a second insulating layer on the conductive layer; (4) forming a third insulating layer on the second insulating layer; (5) selectively removing portions of the third insulating layer, the second insulating layer and the conductive layer to form a stacked over-sized gate pattern; (6) forming a first impurity region in the semiconductor substrate utilizing the stacked over-sized gate pattern as a mask; (7) selectively removing an edge portion of the second insulating layer with a wet etch from the stacked over-sized gate pattern to form an undercut with respect to the third insulating layer; (8) removing the third insulating layer; (9) etching the conductive layer using the second insulating layer as a mask to form a gate; and (10) forming a second impurity region in the semiconductor substrate.
Claim 3
Dependent Claim
22 words
The process of claim 1, further comprising: (1) forming a fourth insulating layer; and (2) activating the first and second impurity regions.
Claim 4
Dependent Claim
17 words
The process of claim 1, wherein the first insulating layer comprises silicon dioxide formed by thermal oxidation.
Claim 5
Dependent Claim
13 words
The process of claim 1, wherein the conductive layer comprises in-situ doped polysilicon.
Claim 6
Dependent Claim
23 words
The process of claim 1, wherein the second insulating layer comprises silicon nitride and is formed to a thickness of about 500 Å.
Claim 7
Dependent Claim
18 words
The process of claim 1, wherein the third insulating layer comprises silicon oxide formed by a CVD method.
Claim 8
Dependent Claim
18 words
The process of claim 1, wherein the second and third insulating layers comprise materials having different etch rates.
Claim 9
Dependent Claim
33 words
The process of claim 1, wherein the stacked over-sized gate pattern has a length longer by about 0.2 μm, about 0.1 μm on each side, as compared with the length of the gate.
Claim 10
Dependent Claim
33 words
The process of claim 1, wherein the stacked over-sized gate pattern is formed by sub-steps comprising selectively patterning the third insulating layer and the second insulating layer, and selectively etching the conductive layer.
Claim 11
Dependent Claim
34 words
The process of claim 1, wherein the first impurity region is formed by carrying out an ion implantation using As + ions at a dose of about 1.0×10 15 -1.0×10 16 ions/cm 2 .
Claim 12
Dependent Claim
35 words
The process of claim 1, wherein the wet etching is carried out to remove from the edge of the second insulating layer up to about 0.1 micrometers and comprises dipping into a phosphoric acid solution.
Claim 13
Dependent Claim
34 words
The process of claim 1, wherein the second impurity region is formed by carrying out an ion implantation using phosphorus ions at an ion dose of about 5.0×10 12 -5.0×10 13 ions/cm 2 .
Claim 14
Dependent Claim
37 words
The process of claim 1, wherein the first impurity region is formed by carrying out an ion implantation using B + or BF + ions at a dose of about 1.0×10 15 -1.0×10 16 ions/cm 2 .
Claim 15
Dependent Claim
38 words
The process of claim 1, wherein the second impurity region is formed by carrying out an ion implantation using B + or BF + ions at an ion dose of about 5.0×10 12 -5.0×10 13 ions/cm 2 .
Claim 16
Dependent Claim
25 words
The process of claim 2, wherein the activation of the impurity ions comprises annealing at a temperature of about 870° C. for about 40 minutes.
Claim 17
Dependent Claim
192 words
A process for manufacturing a semiconductor device, comprising the steps of: (1) forming a first insulating layer on a semiconductor substrate; (2) forming a conductive layer on the first insulating layer; (3) forming an upper layer on the conductive layer, wherein the upper layer comprises a material having a different etch rate as compared with the first insulating layer and the conductive layer; (4) forming a second insulating layer on the upper layer, wherein the second insulating layer comprises a material having a different etch rate as compared with the upper layer; (5) selectively removing portions of the second insulating layer, the upper layer and the conductive layer to form a stacked over-sized gate pattern; (6) forming a first impurity region in the semiconductor substrate utilizing the stacked over-sized gate pattern as a mask; (7) selectively removing an edge portion of the upper layer with a wet etch to form an undercut with respect to the second insulating layer; (8) removing the second insulating layer; (9) etching the conductive layer using the upper layer as a mask to form a gate; and (10) forming a second impurity region in the semiconductor substrate.
Claim 18
Dependent Claim
192 words
A process for manufacturing a semiconductor device, comprising the steps of: (1) forming a first insulating layer on a semiconductor substrate; (2) forming a conductive layer on the first insulating layer; (3) forming an upper layer on the conductive layer, wherein the upper layer comprises a material having a different etch rate as compared with the first insulating layer and the conductive layer; (4) forming a second insulating layer on the upper layer, wherein the second insulating layer comprises a material having a different etch rate as compared with the upper layer; (5) selectively removing portions of the second insulating layer, the upper layer and the conductive layer to form a stacked over-sized gate pattern; (6) forming a first impurity region in the semiconductor substrate utilizing the stacked over-sized gate pattern as a mask; (7) selectively removing an edge portion of the upper layer with a wet etch to form an undercut with respect to the second insulating layer; (8) removing the second insulating layer; (9) etching the conductive layer using the upper layer as a mask to form a gate; and (10) forming a second impurity region in the semiconductor substrate.
Claim 19
Dependent Claim
25 words
The process of claim 16, further comprising the steps of: (1) forming a third insulating layer; and (2) activating the first and second impurity regions.
Claim 20
Dependent Claim
16 words
The process of claim 16, wherein the upper layer comprises a metal for forming a silicide.
Claim 21
Dependent Claim
12 words
The process of claim 16, wherein the upper layer comprises a silicide.
Claim 22
Dependent Claim
38 words
The process of claim 16, wherein the wet etch is carried out to remove the edge portion of the upper layer up to about 0.1 micrometers and comprises dipping into an NH 4 OH/H 2 O 2 solution.
Claim 23
Dependent Claim
24 words
The process of claim 16, wherein the stacked over-sized gate pattern has a length about 0.2 micrometers greater than the length of the gate.
References Cited (Backward Citations)
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