US5602770A
Expired / Lapsed
US
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Associative memory device
Assignee: Kawasaki Microelectronics Inc
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Filing: 1996-02-02
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Granted: 1997-02-11
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Expires: 2016-02-02
Abstract
Abstract An associative memory device of the present invention capable of operation at high speed and a reduced power consumption comprises: a memory array; precharge circuits each provided for each pair of a data line and an inverted data line in the memory array to precharge the data lines and the inverted data lines to a precharge potential in a standby mode before at least a data retrieval operation; and data line drivers each provided for the each pair of the data line and the inverted data line to drive the data lines and the inverted data lines to one of a HIGH logic level and a LOW logic level at least in the data retrieval mode, wherein the precharge potential of the data lines and the inverted data lines is lower than a supply potential and higher than a ground potential, preferably, a middle potential between the supply potential and the ground potential.
Inventors
- 👤 Tsuyoshi Ohira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:56
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C15/00; G11C15/04; G11C5/00; G11C5/14
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
145 words
An associative memory device comprising: a memory array comprising a plurality of associative memory cells arranged in rows and columns, and pairs of a data line and an inverted data line, each pair for each column of the memory array; precharge circuits each provided for each pair of the data line and the inverted data line to precharge the data lines and the inverted data lines to a precharge potential in a standby mode before at least a data retrieval mode; and data line drivers each provided for the each pair of the data line and the inverted data line to drive the data lines and the inverted data lines to one of a HIGH logic level and a LOW logic level at least in the data retrieval mode; wherein the precharge potential is lower than a supply potential and higher than a ground potential.
Claim 2
Dependent Claim
145 words
An associative memory device comprising: a memory array comprising a plurality of associative memory cells arranged in rows and columns, and pairs of a data line and an inverted data line, each pair for each column of the memory array; precharge circuits each provided for each pair of the data line and the inverted data line to precharge the data lines and the inverted data lines to a precharge potential in a standby mode before at least a data retrieval mode; and data line drivers each provided for the each pair of the data line and the inverted data line to drive the data lines and the inverted data lines to one of a HIGH logic level and a LOW logic level at least in the data retrieval mode; wherein the precharge potential is lower than a supply potential and higher than a ground potential.
Claim 3
Dependent Claim
26 words
An associative memory device according to claim 1, further comprising a data line potential generator to generate and supply the precharge potential to the precharge circuits.
Claim 4
Dependent Claim
27 words
An associative memory device according to claim 1, wherein each of the data line driver and each of the precharge circuit are united in an integral unit.
Claim 5
Dependent Claim
58 words
An associative memory device according to claim 1, further comprising data line level control circuits each provided for the each pair of the data line and the inverted data line to prevent formation of a deviation of absolute values of incremental voltages from the precharge potential in the pair of the data line and the inverted data line.
Claim 6
Dependent Claim
70 words
An associative memory device according to claim 4, wherein the precharge circuits precharge the data lines and the inverted data lines to the precharge potential also in a standby mode before a read mode; and the data line level control circuits prevents formation of the deviation of the absolute values of the incremental voltages in the pair of the data line and the inverted data line during the read mode.
Claim 7
Dependent Claim
27 words
An associative memory device according to claim 1, wherein the precharge potential is substantially equal to a middle potential between a supply potential and a ground potential.
Claim 8
Dependent Claim
23 words
An associative memory device according to claim 1, wherein the associative memory cells include one of a SRAM cell and a ROM cell.
Claim 9
Dependent Claim
38 words
An associative memory device according to claim 1, wherein both of the each pair of the data line and the inverted data line are connected to all of the cells in the corresponding column of the memory array.
Claim 10
Dependent Claim
115 words
An associative memory device comprising: a memory array comprising a plurality of associative memory cells arranged in rows and columns, and pairs of a data line and an inverted data line, each pair for each column of the memory array; precharging means for precharging the data lines and the inverted data lines to a precharge potential in a standby mode before at least a data retrieval mode; and driving means for driving the data lines and the inverted data lines to one of a HIGH logic level and a LOW logic level at least in the data retrieval mode; wherein the precharge potential is lower than a supply potential and higher than a ground potential.
Claim 11
Dependent Claim
115 words
An associative memory device comprising: a memory array comprising a plurality of associative memory cells arranged in rows and columns, and pairs of a data line and an inverted data line, each pair for each column of the memory array; precharging means for precharging the data lines and the inverted data lines to a precharge potential in a standby mode before at least a data retrieval mode; and driving means for driving the data lines and the inverted data lines to one of a HIGH logic level and a LOW logic level at least in the data retrieval mode; wherein the precharge potential is lower than a supply potential and higher than a ground potential.
Claim 12
Dependent Claim
25 words
An associative memory device according to claim 9, further comprising precharge potential generating means for generating and supplying the precharge potential to the precharging means.
Claim 13
Dependent Claim
22 words
An associative memory device according to claim 9, wherein the driving means and the precharging means are united in an integral unit.
Claim 14
Dependent Claim
27 words
An associative memory device according to claim 9, wherein the precharge potential is substantially equal to a middle potential between a supply potential and a ground potential.
Claim 15
Dependent Claim
23 words
An associative memory device according to claim 9, wherein the associative memory cells include one of a SRAM cell and a ROM cell.
Claim 16
Dependent Claim
150 words
An associative memory device comprising: a memory array comprising a plurality of associative memory cells arranged in rows and columns, and pairs of a data line and an inverted data line, each pair for each column of the memory array; precharge circuits each provided for each pair of the data line and the inverted data line to precharge the data lines and the inverted data lines to a precharge potential in a standby mode before at least a data retrieval mode; and data line drivers each provided for the each pair of the data line and the inverted data line to drive the data lines and the inverted data lines to one of a HIGH logic level and a LOW logic level at least in the data retrieval mode; wherein the precharge potential is substantially equal to a middle potential between the HIGH logic level and the LOW logic level.
Claim 17
Dependent Claim
150 words
An associative memory device comprising: a memory array comprising a plurality of associative memory cells arranged in rows and columns, and pairs of a data line and an inverted data line, each pair for each column of the memory array; precharge circuits each provided for each pair of the data line and the inverted data line to precharge the data lines and the inverted data lines to a precharge potential in a standby mode before at least a data retrieval mode; and data line drivers each provided for the each pair of the data line and the inverted data line to drive the data lines and the inverted data lines to one of a HIGH logic level and a LOW logic level at least in the data retrieval mode; wherein the precharge potential is substantially equal to a middle potential between the HIGH logic level and the LOW logic level.
References Cited (Backward Citations)
US4144589A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |