US5602513A
Expired / Lapsed
US
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Reversed phase-locked loop
Assignee: Canon Inc
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Filing: 1995-06-06
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Granted: 1997-02-11
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Expires: 2015-06-06
Abstract
Abstract A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal.In addition, a selective grounding network is connected to the reference oscillator input of the PLL frequency synthesizer to greatly reduce power consumption of the PLL frequency synthesizer, and as part of the same effort, a voltage switch is utilized to remove power to the VCO.
Inventors
- 👤 John P. De Loe, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:38
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
75 words
A phase-locked loop circuit comprising: means responsive to a control signal for oscillating to produce a loop signal at a first frequency with a phase controlled by the control signal, means coupled to said oscillating means responsive to the loop signal and a reference signal for both generating the control signal and buffering the loop signal to produce a controlled buffered output signal, and means for selectively reducing power consumption of said phase-locked loop circuit.
Claim 2
Dependent Claim
75 words
A phase-locked loop circuit comprising: means responsive to a control signal for oscillating to produce a loop signal at a first frequency with a phase controlled by the control signal, means coupled to said oscillating means responsive to the loop signal and a reference signal for both generating the control signal and buffering the loop signal to produce a controlled buffered output signal, and means for selectively reducing power consumption of said phase-locked loop circuit.
Claim 3
Dependent Claim
17 words
The circuit of claim 1, wherein said power reducing means is coupled to said generating buffering means.
Claim 4
Dependent Claim
16 words
The circuit of claim 1, wherein said power reducing means is coupled to said oscillating means.
Claim 5
Dependent Claim
39 words
The circuit of claim 1, wherein said power reducing means includes a selective grounding network coupled to said generating buffering means, and a switch for removing power to said oscillating means, said switch coupled to said selective grounding network.
Claim 6
Dependent Claim
22 words
The circuit of claim 1, wherein said power reducing means is responsive to a mode select signal in a dual mode telephone.
Claim 7
Dependent Claim
103 words
The circuit of claim 1, wherein said oscillating means includes means coupled to said generating buffering means for filtering the control signal received from said generating buffering means, said filtering means including a low pass filter, and means coupled to said filtering means for controllably oscillating at a frequency determined by a voltage from said filtering means, said controllably oscillating means including a voltage-controlled oscillator responsive to the control signal; and wherein said generating buffering means, contained in a single integrated circuit, includes means for detecting phase differences between the reference signal and the loop signal, and means for buffering the loop signal.
Claim 8
Dependent Claim
134 words
The circuit of claim 6, wherein said generating buffering means includes a phase-locked loop frequency synthesizer including an internal buffer, means for receiving and storing configuration data, means for saving the configuration data when said power reducing means reduces power consumption, means for generating, responsive to the configuration data, the control signal, means for dividing the loop signal down to a divided loop signal, means for dividing the reference signal down to a divided reference signal, means for detecting phase differences between the divided loop signal and the divided reference signal, means for generating the control signal based upon phase differences between the divided loop signal and the divided reference signal, means for detecting phase equivalence between the divided loop signal and the divided reference signal, and means for generating a lock detect signal.
Claim 9
Dependent Claim
59 words
The circuit of claim 7, wherein said generating buffering means further includes means for generating the lock detect signal responsive to detecting phase equivalence between the divided loop signal and the divided reference signal, and means responsive to operation of said power reducing means for generating a false lock detect signal as a substitute for the lock detect signal.
Claim 10
Dependent Claim
30 words
The circuit of claim 8, wherein the false lock detect signal occurs in a frequency modulation (FM) mode in a code division multiple access/frequency modulation (CDMA/FM) dual mode cellular telephone.
Claim 11
Dependent Claim
69 words
A phase-locked loop circuit comprising: means responsive to a control signal for oscillating to produce a loop signal at a first frequency with a phase controlled by the control signal; and means coupled to said oscillating means responsive to the loop signal and a reference signal for, in single, separate integrated circuit, both generating the control signal and buffering the loop signal to produce a controlled buffered output signal.
Claim 12
Dependent Claim
69 words
A phase-locked loop circuit comprising: means responsive to a control signal for oscillating to produce a loop signal at a first frequency with a phase controlled by the control signal; and means coupled to said oscillating means responsive to the loop signal and a reference signal for, in single, separate integrated circuit, both generating the control signal and buffering the loop signal to produce a controlled buffered output signal.
Claim 13
Dependent Claim
18 words
The circuit of claim 10, wherein the loop signal and the reference signal follow different electrical signal paths.
Claim 14
Dependent Claim
97 words
The circuit of claim 10, wherein said oscillating means includes means coupled to said generating buffering means for filtering the control signal received from said generating buffering means, said filtering means including a low pass filter, and means coupled to said filtering means for controllably oscillating at a frequency determined by a voltage from said filtering means, said controllably oscillating means including a voltage-controlled oscillator responsive to the control signal; and wherein said generating buffering means includes means for detecting phase differences between the reference signal and the loop signal, and means for buffering the loop signal.
Claim 15
Dependent Claim
52 words
The circuit of claim 10, further comprising means for selectively reducing power consumption of said phase-locked loop circuit, wherein said power reducing means includes a selective grounding network coupled to said generating buffering means, and a switch for removing power to said oscillating means, said switch coupled to said selective grounding network.
Claim 16
Dependent Claim
22 words
The circuit of claim 13, wherein said power reducing means is responsive to a mode select signal in a dual mode telephone.
Claim 17
Dependent Claim
160 words
The circuit of claim 13, wherein said oscillating means includes a low pass filter coupled to a voltage-controlled oscillator responsive to a voltage level of the control signal, and wherein said generating buffering means includes a phase-locked loop frequency synthesizer including: an internal buffer, means for receiving and storing configuration data, means for generating, responsive to the configuration data, the control signal, means for saving the configuration data when said power reducing means reduces the power consumption, means for dividing the loop signal down to a divided loop signal, means for dividing the reference signal down to a divided reference signal, means for detecting phase differences between the divided loop signal and the divided reference signal, means for generating the control signal based upon phase differences between the divided loop signal and the divided reference signal, means for detecting a phase equivalence between the divided loop signal and the divided reference signal, and means for generating a lock detect signal.
Claim 18
Dependent Claim
59 words
The circuit of claim 13, wherein said generating buffering means further includes means for generating a lock detect signal responsive to detecting phase equivalence between the divided loop signal and the divided reference signal, and means responsive to operation of said power reducing means for generating a false lock detect signal as a substitute for the lock detect signal.
Claim 19
Dependent Claim
30 words
The circuit of claim 16, wherein the false lock detect signal occurs in a frequency modulation (FM) mode in a code division multiple access/frequency modulation (CDMA/FM) dual mode cellular telephone.
Claim 20
Dependent Claim
146 words
A phase-locked loop circuit for receiving as input a reference signal at a reference frequency over a reference signal line and producing as output a buffered controlled output signal at a controlled output frequency on a controlled output signal line, said circuit comprising: a buffered phase detector device contained in a single, separate integrated circuit, said buffered phase detector device including: a phase detector including a first phase detector input coupled to said reference signal line, a second phase detector input coupled to a controlled oscillator output line, and a phase detector output coupled to a controlled oscillator control line, and a buffer including a buffer input coupled to said second phase detector input, and a buffer output coupled to said controlled output signal line; and a controlled oscillator loop disposed in electrical continuity between said controlled oscillator control line and said controlled oscillator output line.
Claim 21
Dependent Claim
146 words
A phase-locked loop circuit for receiving as input a reference signal at a reference frequency over a reference signal line and producing as output a buffered controlled output signal at a controlled output frequency on a controlled output signal line, said circuit comprising: a buffered phase detector device contained in a single, separate integrated circuit, said buffered phase detector device including: a phase detector including a first phase detector input coupled to said reference signal line, a second phase detector input coupled to a controlled oscillator output line, and a phase detector output coupled to a controlled oscillator control line, and a buffer including a buffer input coupled to said second phase detector input, and a buffer output coupled to said controlled output signal line; and a controlled oscillator loop disposed in electrical continuity between said controlled oscillator control line and said controlled oscillator output line.
Claim 22
Dependent Claim
20 words
The circuit of claim 18, wherein said controlled oscillator loop includes a low pass loop filter and a voltage-controlled oscillator.
Claim 23
Dependent Claim
21 words
The circuit of claim 18, further comprising power consumption reduction circuitry including means for selectively grounding said controlled oscillator output line.
Claim 24
Dependent Claim
38 words
The circuit of claim 20, wherein said phase-locked loop circuit is in a code division multiple access/frequency modulation (CDMA/FM) dual mode cellular telephone, and said power consumption reduction circuitry reduces power consumption in the frequency modulation (FM) mode.
Claim 25
Dependent Claim
38 words
The circuit of claim 20, wherein said buffered phase detector device includes means for receiving and storing input configuration data, said buffered phase detector device retains input configuration data when said power consumption reduction circuitry reduces power consumption.
Claim 26
Dependent Claim
88 words
The circuit of claim 18, wherein said buffered phase detector device further includes said second phase detector input disposed in electrical continuity between said controlled oscillator output line and said controlled oscillator control line, a first counter disposed in electrical continuity between said reference signal line and said first phase detector input, a second counter disposed in electrical continuity between said controlled oscillator output line and said second phase detector input, counter configuration memory elements, and a lock detector coupled to said first counter and said second counter.
Claim 27
Dependent Claim
14 words
The circuit of claim 18, wherein said buffer is a conventional reference signal buffer.
Claim 28
Dependent Claim
21 words
The circuit of claim 18, wherein said buffered phase detector device includes a multi-stage reference divider configured to divide by one.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |