Trellis coded modulation system for digital television signal

Claim 2

A trellis coded modulator comprising: means for convolutionally coding a first input data bit X 1 , for deriving first and second output bits Z 0 and Z 1 ; means for precoding one or more second input data bits X 2 -X N for deriving respective output bits Z 2 -Z N ; and means for mapping the output bits Z 0 , Z 1 , Z 2 -Z N into corresponding one-dimensional multi-value symbols, wherein said symbols form a phase variant symbol constellation and wherein the output bits Z 0 , Z 1 identify respective subsets of said symbols, each of said subsets comprising two or more equally spaced symbol values, and the output bits Z 1 , Z 2 -Z N identify respective pairs of said symbols, each of said pairs comprising two adjacent symbol values.

Claim 3

The trellis coded modulator of claim 1 wherein said means for precoding comprises means for precoding one second input data bit X 2 for deriving an output bit Z 2 and wherein said means for mapping comprises means for mapping output bits Z 0 , Z 1 , Z 2 into corresponding eight-value symbols, each of said subsets comprising two equally spaced symbol values and the output bits Z 1 , Z 2 identifying said respective pairs of said symbols.

Claim 4

The trellis coded modulator of claim 1 wherein said multi-value symbols comprise symbols having a plurality of distinct amplitude levels.

Claim 5

The trellis coded modulator of claim 3 wherein said amplitude levels are symmetrical about a zero level and including means for offsetting the amplitude of each of said symbols by a predetermined amount for providing a pilot component.

Claim 6

The trellis coded modulator of claim 2 wherein said eight-value symbols comprise symbols having eight distinct amplitude levels.

Claim 7

The trellis coded modulator of claim 1 including means for supplying said input data bits X 1 , X 2 -X N at a predetermined symbol rate and wherein said precoder and convolution coder each include one or more M symbol interval delay elements, whereby said output bits Z 0 , Z 1 , Z 2 -Z N are provided in the form of M interleaved groups of separately coded bits.

Claim 8

The trellis coded modulator of claim 6 wherein M is equal to 12.

Claim 9

The trellis coded modulator of claim 1 wherein the convolution coder comprises a 4-state, rate 1/2, feedback, systematic convolution coder.

Claim 10

The trellis coded modulator of claim 2 wherein said precoder comprises means for modulo-2 adding a current input data bit X 2 with the input data bit X 2 occurring M input data bit intervals prior thereto.

Claim 11

The trellis coded modulator of claim 9 wherein M is equal to 12.

Claim 12

A trellis coded modulator comprising: means for supplying two or more input data bits X 1 , X 2 -X N at a predetermined symbol rate; a first coder including at least one delay element M symbol intervals in length for convolutionally coding input bit X 1 for deriving first and second output bits Z 0 and Z 1 ; a second coder including a delay element M symbol intervals in length for precoding input bits X 2 -X N for deriving respective output bits Z 2 -Z N , the output bits Z 0 , Z 1 , Z 2 -Z N thereby being provided in the form of M interleaved groups of separately coded bits; and means for mapping the output bits Z 0 , Z 1 , Z 2 -Z N into corresponding one-dimensional multi-value symbols each having a different amplitude level, wherein said symbols form a phase variant symbol constellation, the output bits Z 0 , Z 1 identifying respective subsets of said symbols, wherein the difference between the amplitude levels of the symbols of each of said subsets are equal, and the output bits Z 1 , Z 2 -Z N identifying respective pairs of said symbols each comprising two adjacent amplitude levels.

Claim 13

A trellis coded modulator comprising: means for supplying two or more input data bits X 1 , X 2 -X N at a predetermined symbol rate; a first coder including at least one delay element M symbol intervals in length for convolutionally coding input bit X 1 for deriving first and second output bits Z 0 and Z 1 ; a second coder including a delay element M symbol intervals in length for precoding input bits X 2 -X N for deriving respective output bits Z 2 -Z N , the output bits Z 0 , Z 1 , Z 2 -Z N thereby being provided in the form of M interleaved groups of separately coded bits; and means for mapping the output bits Z 0 , Z 1 , Z 2 -Z N into corresponding one-dimensional multi-value symbols each having a different amplitude level, wherein said symbols form a phase variant symbol constellation, the output bits Z 0 , Z 1 identifying respective subsets of said symbols, wherein the difference between the amplitude levels of the symbols of each of said subsets are equal, and the output bits Z 1 , Z 2 -Z N identifying respective pairs of said symbols each comprising two adjacent amplitude levels.

Claim 14

The trellis coded modulator of claim 11 wherein M is equal to 12.

Claim 15

The trellis coded modulator of claim 11 wherein said means for supplying comprises means for supplying two input data bits X 1 , X 2 , said second coder precoding input bit X 2 for deriving an output bit Z 2 and said means for mapping comprising means for mapping output bits Z 0 , Z 1 , Z 2 into corresponding 8-level symbols, the output bits Z 1 , Z 2 identifying respective pairs of said symbols each comprising two adjacent amplitude levels.

Claim 16

A trellis coded modulator comprising: means for convolutionally coding a first input data bit X 1 , for deriving first and second output bits Z 0 and Z 1 ; means for precoding one or more second input data bits X 2 -X N for deriving respective output bits Z 2 -Z N ; means for developing an output signal by mapping the output bits Z 0 , Z 1 , Z 2 -Z N into corresponding one-dimensional multi-value symbols, wherein said symbols form a phase variant symbol constellation and wherein the output bits Z 0 , Z 1 identify respective subsets of said symbols, each of said subsets comprising two or more equally spaced symbol values, and the output bits Z 1 , Z 2 -Z N identify respective pairs of said symbols, each of said pairs comprising two adjacent symbol values; means for inserting a synchronization signal in said output signal at selected time intervals; and means for preventing said means for precoding and said means for convolutionally coding from changing state during said selected time intervals.

Claim 17

A trellis coded modulator comprising: means for convolutionally coding a first input data bit X 1 , for deriving first and second output bits Z 0 and Z 1 ; means for precoding one or more second input data bits X 2 -X N for deriving respective output bits Z 2 -Z N ; means for developing an output signal by mapping the output bits Z 0 , Z 1 , Z 2 -Z N into corresponding one-dimensional multi-value symbols, wherein said symbols form a phase variant symbol constellation and wherein the output bits Z 0 , Z 1 identify respective subsets of said symbols, each of said subsets comprising two or more equally spaced symbol values, and the output bits Z 1 , Z 2 -Z N identify respective pairs of said symbols, each of said pairs comprising two adjacent symbol values; means for inserting a synchronization signal in said output signal at selected time intervals; and means for preventing said means for precoding and said means for convolutionally coding from changing state during said selected time intervals.

Claim 18

The trellis coded modulator of claim 14 wherein said means for precoding comprises means for precoding one second input data bit X 2 for deriving an output bit Z 2 and wherein said means for mapping comprises means for mapping output bits Z 0 , Z 1 , Z 2 into corresponding eight-value symbols, each of said subsets comprising two equally spaced symbol values and the output bits Z 1 , Z 2 identifying said respective pairs of said symbols.

Claim 19

The trellis coded modulator of claim 14 wherein said multi-value symbols comprise symbols having a plurality of distinct amplitude levels.

Claim 20

The trellis coded modulator of claim 16 wherein said amplitude levels are symmetrical about a zero level and including means for offsetting the amplitude of each of said symbols by a predetermined amount for providing a pilot component.

Claim 21

The trellis coded modulator of claim 15 wherein said eight-value symbols comprise symbols having eight distinct amplitude levels.

Claim 22

The trellis coded modulator of claim 14 including means for supplying said input data bits X 1 , X 2 -X N at a predetermined symbol rate and wherein said precoder and convolution coder each include one or more M symbol interval delay elements, whereby said output bits Z 0 , Z 1 , Z 2 -Z N are provided in the form of M interleaved groups of separately coded bits.

Claim 23

The trellis coded modulator of claim 19 wherein M is equal to 12.

Claim 24

The trellis coded modulator of claim 14 wherein the convolution coder comprises a 4-state, rate 1/2, feedback, systematic convolution coder.

Claim 25

The trellis coded modulator of claim 15 wherein said precoder comprises means for modulo-2 adding a current input data bit X 2 with the input data bit X 2 occurring M input data bit intervals prior thereto.

Claim 26

The trellis coded modulator of claim 22 wherein M is equal to 12.

Claim 27

A trellis coded modulator comprising: means for supplying two or more input data bits X 1 , X 2 14 X N at a predetermined symbol rate; a first coder including at least one delay element M symbol intervals in length for convolutionally coding input bit X 1 for deriving first and second output bits Z 0 and Z 1 ; a second coder including a delay element M symbol intervals in length for precoding input bits X 2 -X N for deriving respective output bits Z 2 -Z N , the output bits Z 0 , Z 1 , Z 2 -Z N thereby being provided in the form of M interleaved groups of separately coded bits; and means for developing an output signal by mapping the output bits Z 0 , Z 1 , Z 2 -Z N into corresponding one-dimensional multi-value symbols each having a different amplitude level, wherein said symbols form a phase variant symbol constellation, the output bits Z 0 , Z 1 identifying respective subsets of said symbols, wherein the difference between the amplitude levels of the symbols of each of said subsets are equal, and the output bits Z 1 , Z 2 -Z N identifying respective pairs of said symbols each comprising two adjacent amplitude levels; means for inserting a synchronization signal in said output signal at selected time intervals; and means for preventing said means for precoding and said means for convolutionally coding from changing state during said selected time intervals.

Claim 28

A trellis coded modulator comprising: means for supplying two or more input data bits X 1 , X 2 14 X N at a predetermined symbol rate; a first coder including at least one delay element M symbol intervals in length for convolutionally coding input bit X 1 for deriving first and second output bits Z 0 and Z 1 ; a second coder including a delay element M symbol intervals in length for precoding input bits X 2 -X N for deriving respective output bits Z 2 -Z N , the output bits Z 0 , Z 1 , Z 2 -Z N thereby being provided in the form of M interleaved groups of separately coded bits; and means for developing an output signal by mapping the output bits Z 0 , Z 1 , Z 2 -Z N into corresponding one-dimensional multi-value symbols each having a different amplitude level, wherein said symbols form a phase variant symbol constellation, the output bits Z 0 , Z 1 identifying respective subsets of said symbols, wherein the difference between the amplitude levels of the symbols of each of said subsets are equal, and the output bits Z 1 , Z 2 -Z N identifying respective pairs of said symbols each comprising two adjacent amplitude levels; means for inserting a synchronization signal in said output signal at selected time intervals; and means for preventing said means for precoding and said means for convolutionally coding from changing state during said selected time intervals.

Claim 29

The trellis coded modulator of claim 24 wherein M is equal to 12.

Claim 30

The trellis coded modulator of claim 24 wherein said means for supplying comprises means for supplying two input data bits X 1 , X 2 , said second coder precoding input bit X 2 for deriving an output bit Z 2 and said means for mapping comprising means for mapping output bits Z 0 , Z 1 , Z 2 into corresponding 8-level symbols, the output bits Z 1 , Z 2 identifying respective pairs of said symbols each comprising two adjacent amplitude levels.