US5600650A
Expired / Lapsed
US
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Method and apparatus for synthesizing clock signals for use with an asynchronous transfer mode system having selectable data transmission rates
Assignee: Sun Microsystems Inc
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Filing: 1995-07-07
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Granted: 1997-02-04
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Expires: 2015-07-07
Abstract
Abstract An asynchronous transfer mode (ATM) segmentation and reassembly (SAR) chip is provided for interfacing a host computer with an ATM system having a physical layer (PHY) chip incorporating, for example, a Unified Test and Operations Physical Interface for ATM (UTOPIA) protocol. The PHY chip is capable of operating at both 155 Mbps and 622 Mbps data transmission rates. The UTOPIA protocol requires a clock which is provided by the SAR chip. In an exemplary embodiment described herein, the SAR chip is configured to accommodate both data transmission rates and to synthesize appropriate clock signals for driving the PHY chip which facilitate the clocking out of data and the sampling of data.
Inventors
- 👤 Rasoul M. Oskouy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:21
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5672; H04L2012/5674
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
166 words
In an asynchronous transfer mode interface system for interfacing with an external system, wherein the external system operates to transmit and receive data in synchronization with receive and transmit clock signals, respectively, provided by the interface system, the interface system comprising: a clock generator for generating first and second clock signals for operating in first and second modes, respectively, with the first clock signal having a clock rate twice that of the second signal; a transmission unit for transmitting data to the external system in the first and second modes by driving the external system with a transmit clock which is, respectively, either the first clock signal inverted or the second clock signal; a receiving unit for receiving data from the external system in the first and second modes by driving the external system with a receive clock which is, respectively, either the first clock signal or the second clock signal and for receiving the data from the external system in synchronization with the receive clock.
Claim 2
Dependent Claim
166 words
In an asynchronous transfer mode interface system for interfacing with an external system, wherein the external system operates to transmit and receive data in synchronization with receive and transmit clock signals, respectively, provided by the interface system, the interface system comprising: a clock generator for generating first and second clock signals for operating in first and second modes, respectively, with the first clock signal having a clock rate twice that of the second signal; a transmission unit for transmitting data to the external system in the first and second modes by driving the external system with a transmit clock which is, respectively, either the first clock signal inverted or the second clock signal; a receiving unit for receiving data from the external system in the first and second modes by driving the external system with a receive clock which is, respectively, either the first clock signal or the second clock signal and for receiving the data from the external system in synchronization with the receive clock.
Claim 3
Dependent Claim
13 words
The interface system of claim 1 wherein the external system employs UTOPIA protocol.
Claim 4
Dependent Claim
49 words
The interface system of claim 1 wherein further including a segmentation unit for receiving packets of data from a bus system and for converting the packets to cells of data and a reassembly unit for converting cells of data into packets of data for transmission to the bus system.
Claim 5
Dependent Claim
13 words
The interface system of claim 3 wherein the bus system is an SBus.
Claim 6
Dependent Claim
24 words
The interface system of claim 1 wherein the rates of the first and second clock signals are about 40-50 MHz and 20-25 MHz respectively.
Claim 7
Dependent Claim
23 words
The interface system of claim 5 wherein data transmission rates for the first and second modes are, respectively, 622 Mbps and 155 Mbps.
Claim 8
Dependent Claim
168 words
In an asynchronous transfer mode interface system for interfacing with an external system, wherein the external system operates to transmit and receive data in synchronization with receive and transmit clock signals, respectively, provided by the interface system, a method for transmitting data to, and receiving data from, the external system comprising the steps of: generating first and second clock signals for operating in first and second modes, respectively, with the first clock signal having a clock rate twice that of the second clock signal; transmitting data to the external system in the first and second modes by driving the external system with a transmit clock which is, respectively, either the first clock signal inverted or the second clock signal; receiving data from the external system in the first and second modes by driving the external system with a receive clock which is, respectively, either the first clock signal or the second clock signal and for receiving the data from the external system in synchronization with the receive clock.
Claim 9
Dependent Claim
168 words
In an asynchronous transfer mode interface system for interfacing with an external system, wherein the external system operates to transmit and receive data in synchronization with receive and transmit clock signals, respectively, provided by the interface system, a method for transmitting data to, and receiving data from, the external system comprising the steps of: generating first and second clock signals for operating in first and second modes, respectively, with the first clock signal having a clock rate twice that of the second clock signal; transmitting data to the external system in the first and second modes by driving the external system with a transmit clock which is, respectively, either the first clock signal inverted or the second clock signal; receiving data from the external system in the first and second modes by driving the external system with a receive clock which is, respectively, either the first clock signal or the second clock signal and for receiving the data from the external system in synchronization with the receive clock.
Claim 10
Dependent Claim
13 words
The method of claim 7 wherein the external system employs the UTOPIA protocol.
Claim 11
Dependent Claim
58 words
The method of claim 7 wherein the interface system further performs the steps of receiving packets of data from a bus system and converting the packets of data to cells of data for transmission to the external system; and converting cells of data received from the external system into packets of data for transmission to the bus system.
Claim 12
Dependent Claim
12 words
The method of claim 7 wherein the bus system is an SBus.
Claim 13
Dependent Claim
23 words
The method of claim 7 wherein the rates of the first and second clock signals are about 40-50 MHz and 20-25 MHz respectively.
Claim 14
Dependent Claim
22 words
The method of claim 11 wherein data transmission rates for the first and second modes are, respectively, 622 Mbps and 155 Mbps.
Claim 15
Independent Claim
214 words
A system comprising: a host computer; an asynchronous transfer mode system; an asynchronous transfer mode interface system for interconnecting the computer system and the asynchronous transfer mode system and for providing a transmit clock signal and a receive clock signal to the asynchronous transfer mode system for use in, respectively, transmitting data to, and receiving data from, the asynchronous transfer mode system; a clock generator, within the asynchronous transfer mode interface system, for generating first and second clock signals for operating in first and second modes, respectively, with the first clock signal having a dock rate twice that of the second clock signal; a transmission unit, within the interface system, for transmitting data to the asynchronous transfer mode system in the first and second modes by driving the asynchronous transfer mode system with the transmit clock which is, respectively, either the first clock signal inverted or the second clock signal; and a receiving unit, within the interface system, for receiving data from the asynchronous transfer mode system in the first and second modes by driving the asynchronous transfer mode system with a receive clock which is, respectively, either the first clock signal or the second dock signal and for receiving the data from the asynchronous transfer mode system in synchronization with the receive clock.
Claim 16
Independent Claim
214 words
A system comprising: a host computer; an asynchronous transfer mode system; an asynchronous transfer mode interface system for interconnecting the computer system and the asynchronous transfer mode system and for providing a transmit clock signal and a receive clock signal to the asynchronous transfer mode system for use in, respectively, transmitting data to, and receiving data from, the asynchronous transfer mode system; a clock generator, within the asynchronous transfer mode interface system, for generating first and second clock signals for operating in first and second modes, respectively, with the first clock signal having a dock rate twice that of the second clock signal; a transmission unit, within the interface system, for transmitting data to the asynchronous transfer mode system in the first and second modes by driving the asynchronous transfer mode system with the transmit clock which is, respectively, either the first clock signal inverted or the second clock signal; and a receiving unit, within the interface system, for receiving data from the asynchronous transfer mode system in the first and second modes by driving the asynchronous transfer mode system with a receive clock which is, respectively, either the first clock signal or the second dock signal and for receiving the data from the asynchronous transfer mode system in synchronization with the receive clock.
Claim 17
Dependent Claim
13 words
The system of claim 13 wherein the external system employs a UTOPIA protocol.
Claim 18
Dependent Claim
60 words
The system of claim 13 wherein the interface system further includes a segmentation unit for receiving packets of data from a bus system and for converting to cells of data for transmission to the external system and a reassembly unit for converting cells of data received from the external system into packets of data for transmission to the bus system.
Claim 19
Dependent Claim
12 words
The system of claim 15 wherein the bus system is an SBus.
Claim 20
Dependent Claim
23 words
The system of claim 13 wherein the rates of the first and second clock signals are about 40-50 MHz and 20-25 MHz respectively.
Claim 21
Dependent Claim
22 words
The system of claim 17 wherein data transmission rates for the first and second modes are, respectively, 622 Mbps and 155 Mbps.
Claim 22
Dependent Claim
17 words
The system of claim 13 wherein the asynchronous transfer mode system is a physical layer interface chip.
Claim 23
Dependent Claim
18 words
The system of claim 13 wherein the asynchronous transfer mode interface system is a segmentation and reassembly unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |