US5599745A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method to provide a void between adjacent conducting lines in a semiconductor device
Assignee: Micron Technology Inc
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Filing: 1995-06-07
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Granted: 1997-02-04
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Expires: 2015-06-07
Abstract
Abstract The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier from a void between conductive lines by heating the dielectric. Another method of the invention uses sidewall film to form a similar barrier.
Inventors
- 👤 Alan R. Reinberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:32
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; H10W20/01; H10W20/071; H10W20/072; H10W20/41; H10W20/435; H10W20/45; H10W20/46; H10W20/482; H10W20/483
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
105 words
A method of building a semiconductor device, comprising the steps of: forming a layer of conductive material on a wafer; forming a layer of dielectric material on top of said conductive layer; etching said layer of dielectric material and said layer of conductive material to form a first line and a second line adjacent to said first line, each said line having a conductive section, and a dielectric section disposed upon said conductive section; and heating said wafer until said dielectric sections move toward each other forming a cavity between the conductive section of said first line and the conductive section of said second line.
Claim 2
Independent Claim
105 words
A method of building a semiconductor device, comprising the steps of: forming a layer of conductive material on a wafer; forming a layer of dielectric material on top of said conductive layer; etching said layer of dielectric material and said layer of conductive material to form a first line and a second line adjacent to said first line, each said line having a conductive section, and a dielectric section disposed upon said conductive section; and heating said wafer until said dielectric sections move toward each other forming a cavity between the conductive section of said first line and the conductive section of said second line.
Claim 3
Dependent Claim
25 words
The method of claim 1 further comprising the step of disposing a layer of insulating material upon said wafer after the formation of said cavity.
Claim 4
Dependent Claim
11 words
The method of claim 1 wherein said dielectric material is glass.
Claim 5
Dependent Claim
13 words
The method of claim 1 wherein said dielectric material is an organic material.
Claim 6
Dependent Claim
11 words
The method of claim 1 wherein said conductive material is metal.
Claim 7
Dependent Claim
22 words
The method of claim 1, wherein said dielectric material and said layer of conductive material are etched in a single etching operation.
Claim 8
Independent Claim
108 words
A method of building a semiconductor device, comprising the steps of: forming a layer of conductive material on a wafer; forming a layer of dielectric material on top of said conductive layer; etching said layer of dielectric material and said layer of conductive material to form a first line and a second line in spaced relation to said first line, said first line having a conductive section, and a dielectric section disposed upon said conductive section; and heating said wafer until said dielectric section moves toward said second line defining a cavity between the conductive section of said first line and the conductive section of said second line.
Claim 9
Independent Claim
108 words
A method of building a semiconductor device, comprising the steps of: forming a layer of conductive material on a wafer; forming a layer of dielectric material on top of said conductive layer; etching said layer of dielectric material and said layer of conductive material to form a first line and a second line in spaced relation to said first line, said first line having a conductive section, and a dielectric section disposed upon said conductive section; and heating said wafer until said dielectric section moves toward said second line defining a cavity between the conductive section of said first line and the conductive section of said second line.
Claim 10
Dependent Claim
12 words
The method of claim 7 wherein said conductive material comprises a metal.
Claim 11
Independent Claim
112 words
A method of building a semiconductor device comprising: forming a layer of conductive material on a wafer; forming a layer of photoresist upon said conductive layer; etching said layers of conductive and photoresist materials to form a first line assembly and a second line assembly, each of said first and second line assemblies having a conductive section and a photoresist section disposed thereon, each of said first and second line assemblies also having at least one sidewall, said sidewall carrying a sidewall film; and heating said wafer until said photoresist sections move laterally causing two adjacently oriented sidewall films to move toward each other and form a cavity between said conductive sections.
Claim 12
Independent Claim
112 words
A method of building a semiconductor device comprising: forming a layer of conductive material on a wafer; forming a layer of photoresist upon said conductive layer; etching said layers of conductive and photoresist materials to form a first line assembly and a second line assembly, each of said first and second line assemblies having a conductive section and a photoresist section disposed thereon, each of said first and second line assemblies also having at least one sidewall, said sidewall carrying a sidewall film; and heating said wafer until said photoresist sections move laterally causing two adjacently oriented sidewall films to move toward each other and form a cavity between said conductive sections.
Claim 13
Dependent Claim
19 words
The method of claim 9 further comprising the step of removing said photoresist layer without removing said sidewall film.
Claim 14
Dependent Claim
20 words
The method of claim 10 wherein a down stream dry resist removal tool is used to remove said photoresist layer.
Claim 15
Independent Claim
109 words
A method of forming a semiconductor device, comprising the steps of: providing a substrate; forming a layer of conductive material on said substrate; forming a layer of photoresist material over said conductive layer; forming a pattern of conductive material and photoresist material on said substrate, said pattern comprising a plurality of spaced conductive lines with photoresist over said lines, said patterned materials having side surfaces, defining voids between said patterned materials; forming a film on said side surfaces; heating said wafer until said photoresist changes conformity and moves a portion of said film on said side surfaces to at least partially enclose said voids between said spaced conductive lines.
Claim 16
Independent Claim
109 words
A method of forming a semiconductor device, comprising the steps of: providing a substrate; forming a layer of conductive material on said substrate; forming a layer of photoresist material over said conductive layer; forming a pattern of conductive material and photoresist material on said substrate, said pattern comprising a plurality of spaced conductive lines with photoresist over said lines, said patterned materials having side surfaces, defining voids between said patterned materials; forming a film on said side surfaces; heating said wafer until said photoresist changes conformity and moves a portion of said film on said side surfaces to at least partially enclose said voids between said spaced conductive lines.
Claim 17
Dependent Claim
20 words
The method of claim 12 further comprising the step of removing said photoresist layer without substantially removing said sidewall film.
References Cited (Backward Citations)
JPS6398134A
Cited
JPS6436028A
Cited
JPH01253254A
Cited
JPH01296641A
Cited
US5001079A
Cited
US5192715A
Cited
JPH03252137A
Cited
US5335219A
Cited
US5310700A
Cited
US5324683A
Cited
US5407860A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |