Circuit and method for addressing segment descriptor tables

Claim 2

In a processor having a protected mode of operation in which a computer memory associated with said processor contains global and local descriptor tables addressed by a combination of a base address and an index, said processor having global and local base address registers alternatively to provide said base address, said processor further having a selector for containing said index and a table indicator (TI) bit indicating which of said global and local base address registers is to provide said base address, said processor requiring a time to derive said index and a value of said TI bit and a further time to combine said index and said base address, a base address register predicting circuit to predict which of said global and local base address registers is to provide said base address without having to wait for said processor to derive said value of said TI bit, comprising: TI bit predicting circuitry to generate a predicted value of said TI bit as a function of a prior value of said TI bit; and register access circuitry to access one of said global and local base address registers as a function of said predicted value of said TI bit.

Claim 3

The circuit as recited in claim 1 further comprising comparison circuitry to compare a derived value of said TI bit and said predicted value of said TI bit, said register access circuitry accessing another of said global and local base address registers if said derived value of said TI bit is unequal to said predicted value of said TI bit.

Claim 4

The circuit as recited in claim 2 wherein said comparison circuitry is further operative to invert said predicted value of said TI bit.

Claim 5

The circuit as recited in claim 2 further including descriptor table addressing circuitry, associated with said register access circuitry, to retrieve a segment descriptor from one of said global and local descriptor tables as a function of said base address and said index.

Claim 6

The circuit as recited in claim 2 further comprising computer memory addressing circuitry to address said computer memory as a function of said inverted predicted value of said TI bit.

Claim 7

In a processor having a protected mode of operation in which a computer memory associated with said processor contains global and local descriptor tables addressed by a combination of a base address and an index, said processor having global and local base address registers alternatively to provide said base address, said processor further having a selector for containing said index and a table indicator (TI) bit indicating which of said global and local base address registers is to provide said base address, said processor requiring a time to derive said index and a value of said TI bit and a further time to combine said index and said base address, a base address register predicting circuit to predict which of said global and local base address registers is to provide said base address without having to wait for said processor to derive said value of said TI bit, comprising: TI bit predicting means for generating a predicted value of said TI bit as a function of a prior value of said TI bit; and register access means for accessing one of said global and local base address registers as a function of said predicted value of said TI bit.

Claim 8

In a processor having a protected mode of operation in which a computer memory associated with said processor contains global and local descriptor tables addressed by a combination of a base address and an index, said processor having global and local base address registers alternatively to provide said base address, said processor further having a selector for containing said index and a table indicator (TI) bit indicating which of said global and local base address registers is to provide said base address, said processor requiring a time to derive said index and a value of said TI bit and a further time to combine said index and said base address, a base address register predicting circuit to predict which of said global and local base address registers is to provide said base address without having to wait for said processor to derive said value of said TI bit, comprising: TI bit predicting means for generating a predicted value of said TI bit as a function of a prior value of said TI bit; and register access means for accessing one of said global and local base address registers as a function of said predicted value of said TI bit.

Claim 9

The circuit as recited in claim 6 further comprising comparison means for comparing a derived value of said TI bit and said predicted value of said TI bit, said register access circuitry means accessing another of said global and local base address registers if said derived value of said TI bit is unequal to said predicted value of said TI bit.

Claim 10

The circuit as recited in claim 7 wherein said comparison means is further operative to invert said predicted value of said TI bit.

Claim 11

The circuit as recited in claim 7 further including descriptor table addressing means, associated with said register access means, for retrieving a segment descriptor from one of said global and local descriptor tables as a function of said base address and said index.

Claim 12

The circuit as recited in claim 7 further comprising computer memory addressing means for addressing said computer memory as a function of said inverted predicted value of said TI bit.

Claim 13

In a processor having a protected mode of operation in which a computer memory associated with said processor contains global and local descriptor tables addressed by a combination of a base address and an index, said processor having global and local base address registers alternatively to provide said base address, said processor further having a selector for containing said index and a table indicator (TI) bit indicating which of said global and local base address registers is to provide said base address, said processor requiring a time to derive said index and a value of said TI bit and a further time to combine said index and said base address, a method of predicting which of said global and local base address registers is to provide said base address without having to wait for said processor to derive said value of said TI bit, comprising the steps of: generating a predicted value of said TI bit as a function of a prior value of said TI bit; and accessing one of said global and local base address registers as a function of said predicted value of said TI bit.

Claim 14

In a processor having a protected mode of operation in which a computer memory associated with said processor contains global and local descriptor tables addressed by a combination of a base address and an index, said processor having global and local base address registers alternatively to provide said base address, said processor further having a selector for containing said index and a table indicator (TI) bit indicating which of said global and local base address registers is to provide said base address, said processor requiring a time to derive said index and a value of said TI bit and a further time to combine said index and said base address, a method of predicting which of said global and local base address registers is to provide said base address without having to wait for said processor to derive said value of said TI bit, comprising the steps of: generating a predicted value of said TI bit as a function of a prior value of said TI bit; and accessing one of said global and local base address registers as a function of said predicted value of said TI bit.

Claim 15

The method as recited in claim 11 further comprising the steps of: comparing a derived value of said TI bit and said predicted value of said TI bit; and accessing another of said global and local base address registers if said derived value of said TI bit is unequal to said predicted value of said TI bit.

Claim 16

The method as recited in claim 12 further comprising the step of inverting said predicted value of said TI bit if said derived value of said TI bit is unequal to said predicted value of said TI bit.

Claim 17

The method as recited in claim 13 further comprising the step of addressing said computer memory as a function of said predicted value of said TI bit.

Claim 18

The method as recited in claim 12 further comprising the step of retrieving a segment descriptor from one of said global and local descriptor tables as a function of said base address and said index.

Claim 19

A computer system, comprising: (a) a processor having a protected mode of operation in which a computer memory associated with said processor contains global and local descriptor tables addressed by a combination of a base address and an index, said processor having global and local base address registers alternatively to provide said base address, said processor further having a selector for containing said index and a table indicator (TI) bit indicating which of said global and local base address registers is to provide said base address, said processor requiring a time to derive said index and a value of said TI bit and a further time to combine said index and said base address; (b) said computer memory further containing instructions including instructions affecting said selector; (c) said processor including instruction fetch logic that fetches instructions from said computer memory; and (d) said processor further including a base address register predicting circuit to predict which of said global and local base address registers is to provide said base address without having to wait for said processor to derive said value of said TI bit, said base address register predicting circuit comprising: (i) TI bit predicting circuitry to generate a predicted value of said TI bit as a function of a prior value of said TI bit; and (ii) register access circuitry to access one of said global and local base address registers as a function of said predicted value of said TI bit.

Claim 20

A computer system, comprising: (a) a processor having a protected mode of operation in which a computer memory associated with said processor contains global and local descriptor tables addressed by a combination of a base address and an index, said processor having global and local base address registers alternatively to provide said base address, said processor further having a selector for containing said index and a table indicator (TI) bit indicating which of said global and local base address registers is to provide said base address, said processor requiring a time to derive said index and a value of said TI bit and a further time to combine said index and said base address; (b) said computer memory further containing instructions including instructions affecting said selector; (c) said processor including instruction fetch logic that fetches instructions from said computer memory; and (d) said processor further including a base address register predicting circuit to predict which of said global and local base address registers is to provide said base address without having to wait for said processor to derive said value of said TI bit, said base address register predicting circuit comprising: (i) TI bit predicting circuitry to generate a predicted value of said TI bit as a function of a prior value of said TI bit; and (ii) register access circuitry to access one of said global and local base address registers as a function of said predicted value of said TI bit.

Claim 21

The computer system as recited in claim 16 further comprising comparison circuitry to compare a derived value of said TI bit and said predicted value of said TI bit, said register access circuitry accessing another of said global and local base address registers if said derived value of said TI bit is unequal to said predicted value of said TI bit.

Claim 22

The computer system as recited in claim 17 wherein said comparison circuitry is further operative to invert said predicted value of said TI bit.

Claim 23

The computer system as recited in claim 17 further including descriptor table addressing circuitry, associated with said register access circuitry, to retrieve a segment descriptor from one of said global and local descriptor tables as a function of said base address and said index.

Claim 24

The computer system as recited in claim 17 further comprising computer memory addressing circuitry to address said computer memory as a function of said inverted predicted value of said TI bit.

Claim 27

The method recited in claim 21 wherein said predicting step further includes the steps of: generating a predicted value of said TI bit as a function of a prior value of said TI bit; and accessing one of said global and local base address registers as a function of said predicted value of said TI bit.

Claim 28

The method as recited in claim 21 further comprising the steps of: comparing a derived value of said TI bit and said predicted value of said TI bit; and accessing another of said global and local base address registers if said derived value of said TI bit is unequal to said predicted value of said TI bit.

Claim 29

The method as recited in claim 23 wherein said comparing step includes the step of inverting said predicted value of said TI bit.

Claim 30

The method as recited in claim 24 further comprising the step of addressing said computer memory as a function of said inverted predicted value of said TI bit.

Claim 31

The method as recited in claim 22 further including the step of retrieving a segment descriptor from one of said global and local descriptor tables as a function of said base address and said index.