Semiconductor memory device having dual word line configuration

Claim 2

A semiconductor memory device comprising: a plurality of sub word lines; a plurality of sub word decoders, each connected to one of said sub word lines; a plurality of pairs of main word lines, each pair connected to a number of said sub word decoders; and a plurality of main word decoders, each comprising a fuse circuit including a fuse, each of said main word decoders connected to one of said pairs of main word lines, and each of said main word decoders including means for setting voltages between a respective pair of lines of said pairs of main word lines different from each other in a selection mode and for setting the voltages between a respective pair of lines of said pairs of main word lines the same as each other in a non-selection mode and only when said fuse is melted.

Claim 3

A device as set forth in claim 1, wherein each of said main word decoders comprises a monitoring circuit, connected to said fuse circuit, for monitoring a state of said fuse and generating an output representing said state.

Claim 4

A device as set forth in claim 2, wherein said monitoring circuit has means for being activated only when a respective one of said main word decoders is in a selection mode.

Claim 5

A device as set forth in claim 2, further comprising a logic circuit, connected to said monitoring circuit output of each of said main word decoders, for generating a logic signal representing the state of said fuse of one of said main word decoders.

Claim 6

A semiconductor memory device comprising: a first power supply terminal to which a first power supply voltage is applied; a second power supply terminal to which a second power voltage lower than said first power supply voltage is applied; a third power supply terminal to which a third power voltage lower than said second power supply voltage is applied; a plurality of predecoding lines; a predecoding means, connected to said predecoding lines, for selecting one predecoding line and applying said first power supply voltage thereto; a plurality of sub word lines; a plurality of sub word decoders, each including a first N-channel MOS transistor having a drain connected to one of said predecoding lines, a source connected to one of said sub word lines, and a gate, and a second N-channel MOS transistor having a drain connected to the source of said first N-channel MOS transistor, a source connected to said third power supply terminal; a plurality of pairs of first and second main word lines, said first and second main word lines being connected to the gates of said first and second N-channel MOS transistors, respectively, of a number of said sub word decoders; and a plurality of main word decoders each connected to one of said pairs of main word lines, each of said main word decoders comprising: a first logic circuit for receiving an address signal to generate a selection signal; a second logic circuit, connected between said first logic circuit and said first main word line, for applying said first power supply voltage to said first main word line when said selection signal is active and applying said third power supply voltage to said first main word line when said selection signal is inactive; a third logic circuit, connected between said first logic circuit and said second main word line, for applying said third power supply voltage to said first main word line when said selection signal is active and applying said second power supply voltage to said first main word line when said selection signal is inactive; and a fuse circuit, connected to said third logic circuit, for disabling said third logic circuit to apply said third power supply voltage to said second main word line when said fuse of said fuse circuit is melted.

Claim 7

A semiconductor memory device comprising: a first power supply terminal to which a first power supply voltage is applied; a second power supply terminal to which a second power voltage lower than said first power supply voltage is applied; a third power supply terminal to which a third power voltage lower than said second power supply voltage is applied; a plurality of predecoding lines; a predecoding means, connected to said predecoding lines, for selecting one predecoding line and applying said first power supply voltage thereto; a plurality of sub word lines; a plurality of sub word decoders, each including a first N-channel MOS transistor having a drain connected to one of said predecoding lines, a source connected to one of said sub word lines, and a gate, and a second N-channel MOS transistor having a drain connected to the source of said first N-channel MOS transistor, a source connected to said third power supply terminal; a plurality of pairs of first and second main word lines, said first and second main word lines being connected to the gates of said first and second N-channel MOS transistors, respectively, of a number of said sub word decoders; and a plurality of main word decoders each connected to one of said pairs of main word lines, each of said main word decoders comprising: a first logic circuit for receiving an address signal to generate a selection signal; a second logic circuit, connected between said first logic circuit and said first main word line, for applying said first power supply voltage to said first main word line when said selection signal is active and applying said third power supply voltage to said first main word line when said selection signal is inactive; a third logic circuit, connected between said first logic circuit and said second main word line, for applying said third power supply voltage to said first main word line when said selection signal is active and applying said second power supply voltage to said first main word line when said selection signal is inactive; and a fuse circuit, connected to said third logic circuit, for disabling said third logic circuit to apply said third power supply voltage to said second main word line when said fuse of said fuse circuit is melted.

Claim 8

A device as set forth in claim 5, wherein each of said main word decoders further comprises a monitoring circuit including: a third N-channel MOS transistor having a drain for generating a fuse melting indicating signal, a gate connected to said fuse circuit, and a source; and a fourth N-channel MOS transistor having a drain connected to the source of said third N-channel MOS transistor, a gate connected to said third logic circuit, and a source connected to said third power supply terminal.

Claim 9

A device as set forth in claim 6, further comprising a fourth logic circuit, connected to the drain of said third N-channel MOS transistor of each of said main word decoders, for generating a logic signal representing the state of said fuse of one of said main word decoders.

Claim 10

A semiconductor memory device comprising: a first power supply terminal to which a first power supply voltage is applied; a second power supply terminal to which a second power supply voltage lower than said first power supply voltage is applied; a third power supply terminal to which a third power supply voltage lower than said second power supply voltage is applied; a plurality of predecoding lines; a predecoding means, connected to said predecoding lines, for selecting one of said predecoding lines and applying said first power supply voltage thereto; a plurality of sub word lines; a plurality of sub word decoders, each including a first N-channel MOS transistor having a drain connected to one of said predecoding lines, and a source connected to one of said sub word lines, and a gate, and a second N-channel MOS transistor having a drain connected to the source of said first N-channel MOS transistor, a source connected to said third power supply terminal; a plurality of pairs of first and second main word lines, said first and second main word lines being connected to the gates of said first and second N-channel MOS transistors, respectively, of a plurality of said sub word decoders; and a plurality of main word decoders each connected to one of said pairs of main word lines, each of said main word decoders comprising: a first logic circuit for receiving an address signal to generate a first selection signal; a second logic circuit for receiving a block selection signal to generate a second selection signal; a third logic circuit, connected to said first and second logic circuits, for generating a third selection signal when said first and second selection signals are both active; a fourth logic circuit, connected between said third logic circuit and said first main word line, for applying said first power supply voltage to said first main word line when said third selection signal is active and applying said third power supply voltage to said first main word line when said third selection signal is inactive; a fifth logic circuit, connected between said third logic circuit and said second main word line, for applying said third power supply voltage to said first main word line when said third selection signal is active and applying said second power supply voltage to said first main word line when said third selection signal is inactive; and a fuse circuit having a fuse; a sixth logic circuit, connected to said fuse circuit, said second logic circuit, and said fifth logic circuit, for disabling said fifth logic circuit to apply said third power supply voltage to said second main word line when said fuse of said fuse circuit is melted and said second selection signal is active.

Claim 11

A semiconductor memory device comprising: a first power supply terminal to which a first power supply voltage is applied; a second power supply terminal to which a second power supply voltage lower than said first power supply voltage is applied; a third power supply terminal to which a third power supply voltage lower than said second power supply voltage is applied; a plurality of predecoding lines; a predecoding means, connected to said predecoding lines, for selecting one of said predecoding lines and applying said first power supply voltage thereto; a plurality of sub word lines; a plurality of sub word decoders, each including a first N-channel MOS transistor having a drain connected to one of said predecoding lines, and a source connected to one of said sub word lines, and a gate, and a second N-channel MOS transistor having a drain connected to the source of said first N-channel MOS transistor, a source connected to said third power supply terminal; a plurality of pairs of first and second main word lines, said first and second main word lines being connected to the gates of said first and second N-channel MOS transistors, respectively, of a plurality of said sub word decoders; and a plurality of main word decoders each connected to one of said pairs of main word lines, each of said main word decoders comprising: a first logic circuit for receiving an address signal to generate a first selection signal; a second logic circuit for receiving a block selection signal to generate a second selection signal; a third logic circuit, connected to said first and second logic circuits, for generating a third selection signal when said first and second selection signals are both active; a fourth logic circuit, connected between said third logic circuit and said first main word line, for applying said first power supply voltage to said first main word line when said third selection signal is active and applying said third power supply voltage to said first main word line when said third selection signal is inactive; a fifth logic circuit, connected between said third logic circuit and said second main word line, for applying said third power supply voltage to said first main word line when said third selection signal is active and applying said second power supply voltage to said first main word line when said third selection signal is inactive; and a fuse circuit having a fuse; a sixth logic circuit, connected to said fuse circuit, said second logic circuit, and said fifth logic circuit, for disabling said fifth logic circuit to apply said third power supply voltage to said second main word line when said fuse of said fuse circuit is melted and said second selection signal is active.

Claim 12

A device as set forth in claim 8, wherein each of said main word decoders further comprises a monitoring circuit including: a third N-channel MOS transistor having a drain for generating a fuse melting indicating signal, a gate connected to said fuse circuit, and a source; and a fourth N-channel MOS transistor having a drain connected to the source of said third N-channel MOS transistor, a gate connected to said third logic circuit, and a source connected to said third power supply terminal.

Claim 13

A device as set forth in claim 9, further comprising a seventh logic circuit, connected to the drain of said third N-channel MOS transistor of each of said main word decoders, for generating a logic signal representing the state of said fuse of one of said main word decoders.