US5595924A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Technique of forming over an irregular surface a polysilicon layer with a smooth surface
Assignee: SanDisk Technologies LLC
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Filing: 1994-12-19
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Granted: 1997-01-21
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Expires: 2014-12-19
Abstract
Abstract Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.
Inventors
- 👤 Jack H. Yuan
- 👤 Gheorghe Samachisa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:52
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/48; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/917; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
92 words
A method of forming a structure on an integrated circuit substrate, comprising the steps of: depositing a layer of field oxide on said substrate, etching channels in said field oxide layer, depositing a layer of polysilicon across the field oxide and the channels to a thickness wherein a top surface of the polysilicon layer is substantially smooth across the channels, oxidizing the polysilicon layer top surface to a uniform depth thereacross, and stripping away the oxidized polysilicon material, thereby to leave a polysilicon layer with a substantially smooth surface across the channels.
Claim 2
Independent Claim
92 words
A method of forming a structure on an integrated circuit substrate, comprising the steps of: depositing a layer of field oxide on said substrate, etching channels in said field oxide layer, depositing a layer of polysilicon across the field oxide and the channels to a thickness wherein a top surface of the polysilicon layer is substantially smooth across the channels, oxidizing the polysilicon layer top surface to a uniform depth thereacross, and stripping away the oxidized polysilicon material, thereby to leave a polysilicon layer with a substantially smooth surface across the channels.
Claim 3
Dependent Claim
50 words
A method according to claim 1, wherein the step of etching channels in said field oxide includes anisotropically etching said field oxide, thereby forming said channels with sharp sidewalls, the method further comprising a step of forming spacers along said sidewalls prior to the step of depositing the polysilicon layer.
Claim 4
Dependent Claim
30 words
A method according to claim 1, which additionally comprises, after the step of stripping away the oxidized polysilicon material, separating the polysilicon layer into an array of floating transistor gates.
Claim 5
Dependent Claim
84 words
A method according to claim 1, wherein the step of etching channels in said field oxide includes orienting said channels with lengths extending in a first direction and being spaced apart in a second direction, said first and second directions being perpendicular to each other, the method further comprising, after the step of stripping away the oxidized polysilicon material, separating the polysilicon layer into a plurality of elongated strips having lengths extending in the second direction and being spaced apart in the first direction.
Claim 6
Dependent Claim
31 words
A method according to claim 1, which additionally comprises the steps of forming a dielectric over the smooth polysilicon layer surface, and thereafter depositing a second polysilicon layer on the dielectric.
Claim 7
Independent Claim
142 words
A method of forming a structure on an integrated circuit substrate, comprising: depositing a layer of dielectric material supported by said substrate, forming channels in the dielectric layer by removing portions thereof according to a pattern, forming a layer of polysilicon material over the dielectric layer and extending into the channels, said polysilicon layer having a thickness T over the dielectric layer such that, if the polysilicon layer was deposited only to said thickness T, the polysilicon layer would have depressions in a top surface thereof over the channels, the polysilicon layer forming step including: depositing said layer of polysilicon to a thickness in excess of T over the dielectric layer until the top surface of the polysilicon no longer contains said depressions, and removing a portion of the polysilicon layer until its thickness over the dielectric layer is equal to T.
Claim 8
Independent Claim
142 words
A method of forming a structure on an integrated circuit substrate, comprising: depositing a layer of dielectric material supported by said substrate, forming channels in the dielectric layer by removing portions thereof according to a pattern, forming a layer of polysilicon material over the dielectric layer and extending into the channels, said polysilicon layer having a thickness T over the dielectric layer such that, if the polysilicon layer was deposited only to said thickness T, the polysilicon layer would have depressions in a top surface thereof over the channels, the polysilicon layer forming step including: depositing said layer of polysilicon to a thickness in excess of T over the dielectric layer until the top surface of the polysilicon no longer contains said depressions, and removing a portion of the polysilicon layer until its thickness over the dielectric layer is equal to T.
Claim 9
Dependent Claim
27 words
A method according to claim 6, wherein removing a portion of the polysilicon layer includes oxidizing the polysilicon layer top surface, and stripping away the oxidized polysilicon.
Claim 10
Dependent Claim
42 words
A method according to claim 6, which additionally comprises forming a second dielectric layer over a top surface of the polysilicon layer after the portion thereof has been removed, and thereafter forming a second layer of polysilicon on the second dielectric layer.
References Cited (Backward Citations)
US4267632A
Cited
US5141888A
Cited
US4849369A
Cited
US4818725A
Cited
JPH01120062A
Cited
US5095344A
Cited
US5070032A
Cited
US5343063A
Cited
JPH04299838A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |