Processor unit for a parallel processor system discards a received packet when a reception buffer has insufficient space for storing the packet

Claim 2

A parallel processor system, comprising: a plurality of processor units; and a network for interconnecting said plurality of processor units and transferring packets of data therebetween, each said processor unit comprising: an instruction processor for executing an instruction; a main storage for storing instructions and data; a transmission unit responsive to an instruction of said instruction processor for reading data from said main storage and transmitting said packets to said network, each of said packets containing data and a packet header; and a reception unit for receiving ones of said packets transmitted to said network and writing said received ones of said packets in a reception buffer formed in said main storage, and said reception unit comprising: a reception buffer controller for judging whether an area of said reception buffer has a space sufficient for storing said received ones of said packets; and a packet discard circuit for discarding said data in said received ones of said packets without writing said data in said reception buffer, if said reception buffer controller judges that said reception buffer has an area of a size insufficient for storing said data in said received ones of said packets; wherein said reception unit includes means for storing an instruction of whether a discard is performed or not, said instruction being capable of being externally set; and said packet discard circuit includes a circuit for discarding said received ones of said packets if said means for storing said instruction of performing a discard.

Claim 3

A parallel processor system according to claim 1, wherein said instruction of whether a discard is performed or not is set by said instruction processor.

Claim 4

A parallel processor system according to claim 2, further including an operating system (OS) respectively controlling each said instruction processor and wherein said instruction of whether discard is performed or not is set by said instruction processor in response to an instruction issued by said OS.

Claim 5

A parallel processor system according to claim 2, wherein said reception unit further includes a packet write suspending circuit for suspending said data in said received ones of said packets until said area is formed in said reception buffer and writing said data in said received ones of said packets in said main storage when said area is formed, if said reception buffer controller judges that said area of said reception buffer has a size sufficient for storing said data in said received ones of said packets and if said stored instruction of whether discard is performed does not indicate discard.

Claim 6

A parallel processor system according to claim 3, wherein said reception unit further includes a packet write suspending circuit for suspending said data in said received ones of said packets until said area is formed in said reception buffer and writing said data in said received ones of said packets in said main storage when said area is formed, if said reception buffer controller judges that said area of said reception buffer has a size sufficient for storing said data in said received ones of said packets and if said stored instruction of whether discard is performed does not indicate discard.

Claim 7

A parallel processor system according to claim 1, wherein said reception unit further includes a packet write suspending circuit for suspending said data in said received ones of said packets until said area is formed in said reception buffer and writing said data in said received ones of said packets in said main storage when said area is formed, if said reception buffer controller judges that said area of said reception buffer has a size insufficient for storing said data in said received ones of said packets and if said stored instruction of whether discard is performed does not indicate discard.

Claim 8

A parallel processor system according to claim 6, further including an operating system (OS) respectively controlling each said instruction processor and wherein: said reception unit further includes a circuit for issuing an interrupt to said OS, if said reception buffer controller judges that said area of said reception buffer has a size insufficient for storing said data in said received packet, said packet discard circuit includes a circuit for discarding said received ones of said packets in response to when said OS outputs a packet discard instruction in response to said interrupt; and said packet write suspending circuit includes a circuit for suspending writing said data in said received ones of said packets after said interrupt is issued to said OS and until said OS outputs a packet discard instruction or a packet non-discard instruction, releasing a suspension of writing said data if said OS outputs the packet discard instruction in response to said interrupt, and continuing a suspension of writing said data if said OS outputs the packet non-discard instruction in response to said interrupt.

Claim 9

A parallel processor system according to claim 1, wherein said reception unit further includes a packet write suspending circuit for suspending said data in said received ones of said packets until said area is formed in said reception buffer and writing said data in said received ones of said packets in said main storage when said area is formed, if said reception buffer controller judges that said area of said reception buffer has a size sufficient for storing said data in said received ones of said packets and if said stored instruction of whether discard is performed does not indicate discard.

Claim 10

A parallel processor system, comprising: a plurality of processor units; and a network for interconnecting said plurality of processor units and transferring packets of data therebetween, each said processor unit comprising: an instruction processor for executing an instruction; a main storage for storing instructions and data; a transmission unit responsive to an instruction of said instruction processor for reading data from said main storage and transmitting said packets to said network, each of said packets containing data and a packet header; and a reception unit for receiving ones of said packets transmitted to said network and writing said received ones of said packets in a reception buffer formed in said main storage, and said reception unit comprising: a reception buffer controller for judging whether an area of said reception buffer has a space sufficient for storing said received ones of said packets; a packet discard circuit for discarding said data in said received ones of said packets without writing said data in said reception buffer if said reception buffer controller judges that said reception buffer has an area of a size insufficient for storing said data in said received ones of said packets; and an operating system (OS) respectively controlling each said instruction processor; wherein said reception unit further includes a circuit for issuing an interrupt to said OS if said reception buffer controller judges that said area of said reception buffer has a size insufficient for storing said data in said received packet; and said packet discard circuit includes a circuit for discarding said received ones of said packets in response to when said OS outputs a packet discard instruction in response to said interrupt.

Claim 11

A parallel processor system, comprising: a plurality of processor units; and a network for interconnecting said plurality of processor units and transferring packets of data therebetween, each said processor unit comprising: an instruction processor for executing an instruction; a main storage for storing instructions and data; a transmission unit responsive to an instruction of said instruction processor for reading data from said main storage and transmitting said packets to said network, each of said packets containing data and a packet header; and a reception unit for receiving ones of said packets transmitted to said network and writing said received ones of said packets in a reception buffer formed in said main storage, and said reception unit comprising: a reception buffer controller for judging whether an area of said reception buffer has a space sufficient for storing said received ones of said packets; a packet discard circuit for discarding said data in said received ones of said packets without writing said data in said reception buffer if said reception buffer controller judges that said reception buffer has an area of a size insufficient for storing said data in said received ones of said packets; and an operating system (OS) respectively controlling each said instruction processor; wherein said reception unit further includes a circuit for issuing an interrupt to said OS if said reception buffer controller judges that said area of said reception buffer has a size insufficient for storing said data in said received packet; and said packet discard circuit includes a circuit for discarding said received ones of said packets in response to when said OS outputs a packet discard instruction in response to said interrupt.

Claim 12

A parallel processor system according to claim 9, wherein said reception unit further includes a packet write suspending circuit for suspending said data in said received ones of said packets until said area is formed in said reception buffer and writing said data in said received ones of said packets in said main storage when said area is formed, if said reception buffer controller judges that said area of said reception buffer has a size sufficient for storing said data in said received ones of said packets and if said stored instruction of whether discard is performed does not indicate discard.

Claim 13

A parallel processor system, comprising: a plurality of processor units; and a network for interconnecting said plurality of processor units and transferring packets of data therebetween, each said processor unit comprising: an instruction processor for executing an instruction; a main storage for storing instructions and data; a transmission unit responsive to an instruction of said instruction processor for reading data from said main storage and transmitting said packets to said network, each of said packets containing data and a packet header; and a reception unit for receiving ones of said packets transmitted to said network and writing said received ones of said packets in a reception buffer formed in said main storage, and said reception unit comprising: a reception buffer controller for judging whether an area of said reception buffer has a space sufficient for storing said received ones of said packets; and a packet discard circuit for discarding said data in said received ones of said packets without writing said data in said reception buffer, if said reception buffer controller judges that said reception buffer has an area of a size insufficient for storing said data in said received ones of said packets; wherein said main storage includes a plurality of reception buffers for storing different types of packets in a discriminating manner; and said reception unit comprises: means for judging a type of said received ones of said packets and means for selecting one of said plurality of reception buffers in which said received ones of said packets is stored; a reception buffer controller provided for each said reception buffer for judging, if said reception buffer is selected by said selecting means to be a reception buffer for storing said received ones of said packets, whether said area of said reception buffer has a size sufficient for storing said received packet; a packet discard circuit for discarding data in said received ones of said packets without writing said data in said selected reception buffer, if said reception buffer controller judges that said selected reception buffer has an area of a size insufficient for storing said data in said received ones of said packets; and a circuit for controlling whether said received ones of said packets is discarded, in accordance with said selected reception buffer.

Claim 14

A parallel processor system, comprising: a plurality of processor units; and a network for interconnecting said plurality of processor units and transferring packets of data therebetween, each said processor unit comprising: an instruction processor for executing an instruction; a main storage for storing instructions and data; a transmission unit responsive to an instruction of said instruction processor for reading data from said main storage and transmitting said packets to said network, each of said packets containing data and a packet header; and a reception unit for receiving ones of said packets transmitted to said network and writing said received ones of said packets in a reception buffer formed in said main storage, and said reception unit comprising: a reception buffer controller for judging whether an area of said reception buffer has a space sufficient for storing said received ones of said packets; and a packet discard circuit for discarding said data in said received ones of said packets without writing said data in said reception buffer, if said reception buffer controller judges that said reception buffer has an area of a size insufficient for storing said data in said received ones of said packets; wherein said main storage includes a plurality of reception buffers for storing different types of packets in a discriminating manner; and said reception unit comprises: means for judging a type of said received ones of said packets and means for selecting one of said plurality of reception buffers in which said received ones of said packets is stored; a reception buffer controller provided for each said reception buffer for judging, if said reception buffer is selected by said selecting means to be a reception buffer for storing said received ones of said packets, whether said area of said reception buffer has a size sufficient for storing said received packet; a packet discard circuit for discarding data in said received ones of said packets without writing said data in said selected reception buffer, if said reception buffer controller judges that said selected reception buffer has an area of a size insufficient for storing said data in said received ones of said packets; and a circuit for controlling whether said received ones of said packets is discarded, in accordance with said selected reception buffer.

Claim 15

A parallel processor system according to claim 11, further including an operating system (OS) respectively controlling each said instruction processor and wherein said control circuit includes: a circuit for issuing an interrupt to said OS, if said reception buffer controller judges that said area of said selected reception buffer has a size insufficient for storing said data in said received ones of said packets; and a circuit for supplying said packet discard circuit with one of a packet discard instruction and a packet non-discard instruction outputted by said OS in response to said interrupt.

Claim 16

A parallel processor system comprising: a plurality of processor units; and a network for interconnecting said plurality of processor units and transferring packets of data between arbitrary processor units; each said processor unit comprising: an instruction processor for executing an instruction having an operating system for controlling operation of said instruction processor; a main storage for storing instructions and data; a transmission unit responsive to an instruction from said instruction processor for reading data from said main storage and transmitting said packets to said network; and a reception unit for writing ones of said packets received from said network into said main storage, said reception unit of each said processor unit comprising: a discard command bit capable of being set by said instruction processor; a reception buffer pointer controller for supervising a reception buffer address of a reception buffer formed on said main storage at which received ones of said packets are written and judging whether an area of said reception buffer has a space sufficient to be written with said ones of said packets; a reception packet discard judging unit for receiving said discard command bit and a notice of presence of said sufficient space in said area in said reception buffer supplied from said reception buffer pointer controller, judging that said received ones of said packets are writable in said reception buffer area if said discard command bit does not indicate discard and if said reception buffer has said sufficient space in said area, judging that said received ones of said packets are not written in said main storage and the operation of said instructions processor stands by while suspending reception of said received ones of said packets if said discard command bit does not indicate discard and if said area of said reception buffer has insufficient space, and judging that said received ones of said packets are not written in said reception buffer area but are discarded if said discard command bit indicates discard; and a circuit for performing a reception process of said received ones of said packets in accordance with a judgment given by said reception packet discard judging unit.

Claim 17

A parallel processor system comprising: a plurality of processor units; and a network for interconnecting said plurality of processor units and transferring packets of data between arbitrary processor units; each said processor unit comprising: an instruction processor for executing an instruction having an operating system for controlling operation of said instruction processor; a main storage for storing instructions and data; a transmission unit responsive to an instruction from said instruction processor for reading data from said main storage and transmitting said packets to said network; and a reception unit for writing ones of said packets received from said network into said main storage, said reception unit of each said processor unit comprising: a discard command bit capable of being set by said instruction processor; a reception buffer pointer controller for supervising a reception buffer address of a reception buffer formed on said main storage at which received ones of said packets are written and judging whether an area of said reception buffer has a space sufficient to be written with said ones of said packets; a reception packet discard judging unit for receiving said discard command bit and a notice of presence of said sufficient space in said area in said reception buffer supplied from said reception buffer pointer controller, judging that said received ones of said packets are writable in said reception buffer area if said discard command bit does not indicate discard and if said reception buffer has said sufficient space in said area, judging that said received ones of said packets are not written in said main storage and the operation of said instructions processor stands by while suspending reception of said received ones of said packets if said discard command bit does not indicate discard and if said area of said reception buffer has insufficient space, and judging that said received ones of said packets are not written in said reception buffer area but are discarded if said discard command bit indicates discard; and a circuit for performing a reception process of said received ones of said packets in accordance with a judgment given by said reception packet discard judging unit.

Claim 18

A parallel processor system according to claim 13, wherein: said transmission unit includes means for adding a reception buffer type to ones of said packets to be transmitted; and said reception unit comprises: a plurality of reception buffer pointer controllers provided in correspondence with reception buffer types; a plurality of discard command bits provided in correspondence with reception buffer types; a plurality of received packet discard judging circuits provided in correspondence with reception buffer types; a circuit for selecting one of said plurality of received packet discard judging circuits corresponding to a reception buffer type of said received ones of said packets; and a circuit for performing a reception process of said received ones of said packets in accordance with a judgment given by said selected received packet discard judging circuit.

Claim 19

A parallel processor system according to claim 13, wherein each said reception unit of said processor unit is provided with a reception process failure detector for detecting that the reception process cannot be performed normally and a received packet discard judging circuit for discarding said received ones of said packets without writing said received ones of said packets in said reception buffer area if said reception process failure detector detects a failure.

Claim 20

A packet discard method for a parallel processor system including a plurality of processor units and a network for interconnecting said plurality of processor units and transferring packets of data between arbitrary processor units alternately functioning in transmission and reception of said packets of data, each said processor unit including an instruction processor for executing an instruction, a main storage for storing instructions and data, a transmission unit responsive to an instruction from said instruction processor for reading data from said main storage and transmitting said data as said packets to said network, each of said packets including said data and a packet header, and a reception unit for writing received ones of said packets from said network into said main storage, said packet discard method comprising the steps of: receiving ones of said packets transferred from a transmission one of said processor units at a reception one of said processor units; judging whether said reception processor unit has an area of sufficient space for storing data in said received ones of said packets; issuing an interrupt to an operating system (OS) which controls said reception processor unit if it is judged that said area has insufficient space for storing said data in said received ones of said packets; judging with said OS whether said received ones of said packets are to be discarded; and discarding said received ones of said packets if said OS judges that said received ones of packets are to be discarded; wherein said OS judges whether said received ones of said packets satisfy a certain packet discard condition, and in accordance with said judgment result, judges whether said received ones of said packets are to be discarded.

Claim 21

A packet discard method for a parallel processor system including a plurality of processor units and a network for interconnecting said plurality of processor units and transferring packets of data between arbitrary processor units alternately functioning in transmission and reception of said packets of data, each said processor unit including an instruction processor for executing an instruction, a main storage for storing instructions and data, a transmission unit responsive to an instruction from said instruction processor for reading data from said main storage and transmitting said data as said packets to said network, each of said packets including said data and a packet header, and a reception unit for writing received ones of said packets from said network into said main storage, said packet discard method comprising the steps of: receiving ones of said packets transferred from a transmission one of said processor units at a reception one of said processor units; judging whether said reception processor unit has an area of sufficient space for storing data in said received ones of said packets; issuing an interrupt to an operating system (OS) which controls said reception processor unit if it is judged that said area has insufficient space for storing said data in said received ones of said packets; judging with said OS whether said received ones of said packets are to be discarded; and discarding said received ones of said packets if said OS judges that said received ones of packets are to be discarded; wherein said OS judges whether said received ones of said packets satisfy a certain packet discard condition, and in accordance with said judgment result, judges whether said received ones of said packets are to be discarded.

Claim 22

A packet discard method for a parallel processor system including a plurality of processor units and a network for interconnecting said plurality of processor units and transferring packets of data between arbitrary processor units alternately functioning in transmission and reception of said packets of data, each said processor unit including an instruction processor for executing an instruction, a main storage for storing instructions and data, a transmission unit responsive to an instruction from said instruction processor for reading data from said main storage and transmitting said data as said packets to said network, each of said packets including said data and a packet header, and a reception unit for writing received ones of said packets from said network into said main storage, said packet discard method comprising the steps of: receiving ones of said packets transferred from a transmission one of said processor units at a reception one of said processor units; judging whether said reception processor unit has an area of sufficient space for storing data in said received ones of said packets; issuing an interrupt to an operating system (OS) which controls said reception processor unit if it is judged that said area has insufficient space for storing said data in said received ones of said packets; judging with said OS whether said received ones of said packets are to be discarded; and discarding said received ones of said packets if said OS judges that said received ones of said packets are discarded; wherein said certain packet discard condition includes a condition regarding a type of said received ones of said packets.

Claim 23

A packet discard method for a parallel processor system including a plurality of processor units and a network for interconnecting said plurality of processor units and transferring packets of data between arbitrary processor units alternately functioning in transmission and reception of said packets of data, each said processor unit including an instruction processor for executing an instruction, a main storage for storing instructions and data, a transmission unit responsive to an instruction from said instruction processor for reading data from said main storage and transmitting said data as said packets to said network, each of said packets including said data and a packet header, and a reception unit for writing received ones of said packets from said network into said main storage, said packet discard method comprising the steps of: receiving ones of said packets transferred from a transmission one of said processor units at a reception one of said processor units; judging whether said reception processor unit has an area of sufficient space for storing data in said received ones of said packets; issuing an interrupt to an operating system (OS) which controls said reception processor unit if it is judged that said area has insufficient space for storing said data in said received ones of said packets; judging with said OS whether said received ones of said packets are to be discarded; and discarding said received ones of said packets if said OS judges that said received ones of said packets are discarded; wherein said certain packet discard condition includes a condition regarding a type of said received ones of said packets.

Claim 24

A packet discard method for a parallel processor system including a plurality of processor units and a network for interconnecting said plurality of processor units and transferring packets of data between arbitrary processor units alternately functioning in transmission and reception of said packets of data, each said processor unit including an instruction processor for executing an instruction, a main storage for storing instructions and data, a transmission unit responsive to an instruction from said instruction processor for reading data from said main storage and transmitting said data as said packets to said network, each of said packets including said data and a packet header, and a reception unit for writing received ones of said packets from said network into said main storage, said packet discard method comprising the steps of: receiving ones of said packets transferred from a transmission one of said processor units at a reception one of said processor units; judging whether said reception processor unit has an area of sufficient space for storing data in said received ones of said packets; issuing an interrupt to an operating system (OS) which controls said reception processor unit if it is judged that said area has insufficient space for storing said data in said received ones of said packets; judging with said OS whether said received ones of said packets are to be discarded; and discarding said received ones of said packets if said OS judges that said received ones of said packets are discarded; wherein if said OS judges that said received ones of said packets are not discarded, said received ones of said packets are held in said reception unit of said reception processor unit until said area has sufficient space.

Claim 25

A packet discard method for a parallel processor system including a plurality of processor units and a network for interconnecting said plurality of processor units and transferring packets of data between arbitrary processor units alternately functioning in transmission and reception of said packets of data, each said processor unit including an instruction processor for executing an instruction, a main storage for storing instructions and data, a transmission unit responsive to an instruction from said instruction processor for reading data from said main storage and transmitting said data as said packets to said network, each of said packets including said data and a packet header, and a reception unit for writing received ones of said packets from said network into said main storage, said packet discard method comprising the steps of: receiving ones of said packets transferred from a transmission one of said processor units at a reception one of said processor units; judging whether said reception processor unit has an area of sufficient space for storing data in said received ones of said packets; issuing an interrupt to an operating system (OS) which controls said reception processor unit if it is judged that said area has insufficient space for storing said data in said received ones of said packets; judging with said OS whether said received ones of said packets are to be discarded; and discarding said received ones of said packets if said OS judges that said received ones of said packets are discarded; wherein if said OS judges that said received ones of said packets are not discarded, said received ones of said packets are held in said reception unit of said reception processor unit until said area has sufficient space.