Frequency controller and method of correcting phase estimates in a PSK demodulator using frequency control

Claim 2

A frequency controller for use in a receiver of a digital communications system, said receiver being capable of receiving a phase shift keyed (PSK) signal representing a sequence of transmitted symbols, each of said transmitted symbols corresponding to one of a set of known phases, said receiver generating phase estimates related to the symbols of the PSK signal so received, said PSK signal being transmitted at a predetermined frequency and said received PSK signal having a frequency with a variable offset from said predetermined frequency, the frequency controller comprising: phase correction means having an input indicative of said variable offset for correcting said phase estimates to produce corrected phase estimates; phase error detection means interfaced with said phase correction means for determining whether at least some of said corrected phase estimates contain a phase error, and if so, for determining for each of those said phase estimates whether said phase estimate has a phase either 1) greater than the known phase corresponding to the symbol of the received PSK signal, or 2) less than the known phase corresponding to the symbol of the received PSK signal; counting means interfaced with said phase error detection means for maintaining a positive count of those phase estimates greater than the corresponding known phase and a negative count of those phase estimates less than the corresponding known phase; and frequency offset means interfaced with said counting means and said phase correction means for generating a frequency offset based on a difference between said positive and negative counts, said frequency offset so generated defining said variable offset used to produce said corrected phase estimates.

Claim 3

The frequency controller of claim 1, wherein said phase error detection means comprises: a phase error detection circuit interfaced with said phase correction means to receive an input of said corrected phase estimates, said error detection circuit comparing said corrected phase estimate with one of said known phases closest in value to said corrected phase to determine an absolute value of the phase error, said phase error detection circuit providing an output representative of said absolute value of said phase estimate and representative of whether said phase error is greater or less than said known phase; and a threshold detector interfaced with said phase error detection circuit and said counting means, said threshold detector comparing said absolute value of the phase error to a predetermined positive threshold when said corrected phase estimate is greater than said known phase and comparing said absolute phase error to a predetermined negative threshold when said corrected phase estimate is less than said known phase, said counting means counting only those positive and negative counts exceeding said positive and negative thresholds respectively.

Claim 4

The frequency controller of claim 1, wherein a number of phase estimates are averaged by said receiver over a period of time to form averaged phase estimates, each average phase estimate being provided as an input to said phase correction means.

Claim 5

The frequency controller of claim 1, wherein said digital communication system is capable of operating in a burst mode so that said PSK signal is received during a designated slot of each burst, said frequency offset means comprising: a subtractor for accepting said positive and negative counts following each slot in which said PSK signal is received and determining the difference between said positive and negative counts to provide an output of the differences, said differences being indicative of a frequency offset of said PSK signal during said slot; a frequency accumulator interfaced with said subtractor for accepting said differences and for accumulating said differences for a predetermined number of bursts to form an accumulated frequency offset value; a frequency threshold comparator interfaced with said frequency accumulator for comparing said accumulated frequency offset value with a predetermined frequency offset threshold and providing an output indicative of said comparison; and a frequency offset generator for adjusting said frequency offset based on said comparison.

Claim 6

The frequency controller of claim 1, wherein said phase error detection means has a symbol timing input indicating that said phase estimate is related to a single symbol of said received PSK signal, said phase error detection means determining said phase error of only those phase estimates coinciding with the symbol timing.

Claim 7

The frequency controller of claim 1, further comprising: a signal quality indicator interfaced with said counting means for accepting an input of said positive and negative counts and for adding said positive and negative counts together to provide an output indicative of the quality of the received PSK signal.

Claim 10

The method of claim 7, wherein said PSK signal is received during a period of time defining a slot, said frequency offset being provided following each slot so received.

Claim 11

The method of claim 9, further comprising the step of: accumulating said frequency offsets so provided for a predetermined number of slots; and comparing an absolute value of said frequency offsets so accumulated with a predetermined offset threshold; said step of adjusting said phase estimates being carried out only if said absolute value of said accumulated frequency offset exceeds said predetermined offset threshold.

Claim 12

The method of claim 7, further comprising the steps of: generating based on said phase estimates and said identified known phase a value indicative of a phase error of said PSK signal so received; said step of incrementing said positive counter being carried out only if said phase error is greater than a predetermined positive phase error threshold and said phase estimate exceeds said identified known phase; and said step of incrementing said negative counter being carried out only if said phase error is greater than a predetermined negative phase error threshold and said phase estimate is less than said identified known phase.

Claim 13

A frequency controller for use in a receiver of a digital communications system, said receiver being capable of receiving a phase shift keyed (PSK) signal representing a sequence of transmitted symbols, each of said transmitted symbols corresponding to one of a set of known phases, said receiver generating phase estimates related to the symbols of the PSK signal so received, said PSK signal being transmitted at a predetermined frequency and said received PSK signal having a frequency with a variable offset from said predetermined frequency, the frequency controller comprising: phase correction means having an input indicative of said variable offset for correcting said phase estimates to produce corrected phase estimates; phase error detection means interfaced with said phase correction means for determining whether at least some of said corrected phase estimates contain a phase error, and if so, for determining for each of those phase estimates whether said phase estimate has a phase either 1) greater than the known phase corresponding to the symbol of the received PSK signal, or 2) less than the known phase corresponding to the symbol of the received PSK signal; counting means interfaced with said phase error detection means for maintaining a positive count of those phase estimates greater than the corresponding known phase and a negative count of those phase estimates less than the corresponding known phase;frequency offset means interfaced with said counting means and said phase correction means for generating a frequency offset based on a difference between said positive and negative counts, said frequency offset so generated defining said variable offset used to produce said corrected phase estimates; and a signal quality indicator interfaced with said counting means for accepting an input of said positive and negative counts and for adding said positive and negative counts together to provide an output indicative of the quality of the received PSK signal.

Claim 14

A frequency controller for use in a receiver of a digital communications system, said receiver being capable of receiving a phase shift keyed (PSK) signal representing a sequence of transmitted symbols, each of said transmitted symbols corresponding to one of a set of known phases, said receiver generating phase estimates related to the symbols of the PSK signal so received, said PSK signal being transmitted at a predetermined frequency and said received PSK signal having a frequency with a variable offset from said predetermined frequency, the frequency controller comprising: phase correction means having an input indicative of said variable offset for correcting said phase estimates to produce corrected phase estimates; phase error detection means interfaced with said phase correction means for determining whether at least some of said corrected phase estimates contain a phase error, and if so, for determining for each of those phase estimates whether said phase estimate has a phase either 1) greater than the known phase corresponding to the symbol of the received PSK signal, or 2) less than the known phase corresponding to the symbol of the received PSK signal; counting means interfaced with said phase error detection means for maintaining a positive count of those phase estimates greater than the corresponding known phase and a negative count of those phase estimates less than the corresponding known phase;frequency offset means interfaced with said counting means and said phase correction means for generating a frequency offset based on a difference between said positive and negative counts, said frequency offset so generated defining said variable offset used to produce said corrected phase estimates; and a signal quality indicator interfaced with said counting means for accepting an input of said positive and negative counts and for adding said positive and negative counts together to provide an output indicative of the quality of the received PSK signal.

Claim 15

The frequency controller of claim 11, wherein said phase error detection means comprises: a phase error detection circuit interfaced with said phase correction means to receive an input of said corrected phase estimates, said error detection circuit comparing said corrected phase estimate with one of said known phases closest in value to said corrected phase to determine an absolute value of the phase error, said phase error detection circuit providing an output representative of said absolute value of said phase estimate and representative of whether said phase error is greater or less than said known phase; and a threshold detector interfaced with said phase error detection circuit and said counting means, said threshold detector comparing said absolute value of the phase error to a predetermined positive threshold when said corrected phase estimate is greater than said known phase and comparing said absolute phase error to a predetermined negative threshold when said corrected phase estimate is less than said known phase, said counting means counting only those positive and negative counts exceeding said positive and negative thresholds respectively.

Claim 16

The frequency controller of claim 11, wherein a number of phase estimates are averaged by said receiver over a period of time to form averaged phase estimates, each average phase estimate being provided as an input to said phase correction means.

Claim 17

The frequency controller of claim 11, wherein said phase error detection means has a symbol timing input indicating that said phase estimate is related to a single symbol of said received PSK signal, said phase error detection means determining said phase error of only those phase estimates coinciding with the symbol timing.