Asynchronous processor access to a switch table in a network with isochronous capability

Claim 2

In a computer-controlled system having a microprocessor operating according to a clock and an updatable table operating asynchronously of said clock, said updatable table outputting control data for controlling data transfer in said system, apparatus for updating said updatable table, comprising: register means for receiving update data from said microprocessor during a first time period at a data rate corresponding to said clock and outputting said update data to said updatable table; means, coupled to said register means, for determining the beginning of a second period of time during which said updatable table is not being used and for updating said updatable table during said second period, asynchronously with said clock, using at least some of said update data.

Claim 3

Apparatus, as claimed in claim 1, further comprising a plurality of shadow registers wherein data stored in said register means at a first storage time is also stored in at least one of said plurality of shadow registers substantially simultaneously with said first storage time.

Claim 4

Apparatus, as claimed in claim 1, wherein said updatable table comprises an updatable transmit table and updatable receive table, and wherein said register means includes at least a transmit holding register for holding data for updating said updatable transmit table and a receive holding register, different from said transmit holding register, for holding data for updating said updatable receive table.

Claim 5

In a computer-controlled system having a microprocessor operating according to a clock and an updatable table operating asynchronously with said clock, said updatable table outputting control data for controlling data transfer in said system, a method for updating said updatable table, comprising: receiving update data in a first register from said microprocessor during a first time period at a data rate corresponding to said clock and outputting said update data to said updatable table; determining the beginning of a second period of time during which said updatable table is not being used and updating said updatable table during said second period of time during which said updatable table is not being used, asynchronously with said clock, using at least some of said update data.

Claim 6

In a computer-controlled system having a microprocessor operating according to a clock and an updatable table operating asynchronously with said clock, said updatable table outputting control data for controlling data transfer in said system, a method for updating said updatable table, comprising: receiving update data in a first register from said microprocessor during a first time period at a data rate corresponding to said clock and outputting said update data to said updatable table; determining the beginning of a second period of time during which said updatable table is not being used and updating said updatable table during said second period of time during which said updatable table is not being used, asynchronously with said clock, using at least some of said update data.

Claim 7

A method, as claimed in claim 4, wherein said update data includes at least one control word, indicating a table update location, and at least one data word, including data to be stored at said update location.

Claim 8

A method, as claimed in claim 5, wherein said update data includes more data words than control words.

Claim 9

A method, as claimed in claim 6, further comprising incrementing said control word by a first amount to provide a new table update location for a subsequent table update.

Claim 10

A method, as claimed in claim 7, wherein said first amount is programmable.

Claim 11

A method, as claimed in claim 4 wherein said update data includes a plurality of words each of said plurality of words having at least one bit indicating whether the word is a control word or a data word.

Claim 12

A method, as claimed in claim 4, wherein said update data includes a plurality of words each of said plurality of words having at least one bit indicating whether the word is the last data word of the update data.

Claim 13

A method, as claimed in claim 4, further comprising notifying said microprocessor when the table update is complete.

Claim 14

A method, as claimed in claim 11, wherein said step of notifying comprises sending an interrupt to said processor.

Claim 15

A method, as claimed in claim 11, wherein, after said microprocessor has written said update data into said first register, said microprocessor is prevented from writing further data into said first register until after said step of notifying.

Claim 16

Apparatus for communicating between at least first and second stations in a data communication system over at least a first link, said data communication system including a plurality of data sources and sinks, at least a first of said sources and sinks configured to receive or transmit data isochronously and a second of said sources and sinks configured to transmit data non-isochronously, the apparatus comprising: at least a first receiver and at least a first transmitter in said first station; said first link coupling said first station with said second station; said second station being coupled to both said first and second of said sources and sinks; a second transmitter in said second station for transmitting data to said first receiver; a first multiplexer in said second station for permitting the transmitting of data from both of said first and second sources and sinks over said first link as first multiplexed data, said multiplexer providing a first, dedicated bandwidth for first data originating from an isochronous source, including at least said first of said sources and sinks; at least a first updatable switchtable in said first station for storing information indicating at least the destination of data; a microprocessor operating according to a first clock, coupled to said updatable switchtable, said updatable switchtable operating according to a second clock asynchronously with said first clock; a register coupled to said microprocessor for receiving update data from said microprocessor during a first time period at a data rate corresponding to said first clock and coupled to said first updatable switchtable for outputting said update data to said first updatable switchtable.

Claim 17

Apparatus for communicating between at least first and second stations in a data communication system over at least a first link, said data communication system including a plurality of data sources and sinks, at least a first of said sources and sinks configured to receive or transmit data isochronously and a second of said sources and sinks configured to transmit data non-isochronously, the apparatus comprising: at least a first receiver and at least a first transmitter in said first station; said first link coupling said first station with said second station; said second station being coupled to both said first and second of said sources and sinks; a second transmitter in said second station for transmitting data to said first receiver; a first multiplexer in said second station for permitting the transmitting of data from both of said first and second sources and sinks over said first link as first multiplexed data, said multiplexer providing a first, dedicated bandwidth for first data originating from an isochronous source, including at least said first of said sources and sinks; at least a first updatable switchtable in said first station for storing information indicating at least the destination of data; a microprocessor operating according to a first clock, coupled to said updatable switchtable, said updatable switchtable operating according to a second clock asynchronously with said first clock; a register coupled to said microprocessor for receiving update data from said microprocessor during a first time period at a data rate corresponding to said first clock and coupled to said first updatable switchtable for outputting said update data to said first updatable switchtable.

Claim 20

A method, as claimed in claim 15, wherein said step of updating comprises: sampling said second clock; providing said sampled second clock to a one-shot circuit whose output indicates the rising edge of said second clock.

Claim 21

A method, as claimed in claim 15, further comprising: waiting up to a predetermined maximum wait time before performing said step of receiving update data if fewer than a predetermined number of update words are contained in said update data.

Claim 22

A method, as claimed in claim 17, wherein said predetermined number of update words is equal to the number of word that can be stored in said holding register.