US5594702A
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Multi-first-in-first-out memory circuit
Assignee: National Semiconductor Corp
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Filing: 1995-06-28
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Granted: 1997-01-14
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Expires: 2015-06-28
Abstract
Abstract A multi-first-in-first-out (henceforth "multi-FIFO") memory circuit in accordance with this invention comprises: (1) a plurality of groups of storage elements, for example, each group corresponds to a first-in-first-out (FIFO) memory (2) a time multiplexed first address generator for generating address signals of a storage element from a first group that is cyclically selected from the plurality of groups by a sequencer included in the first address generator and (3) a second address generator for generating address signals of a number of successive storage elements from a second group that is selected from the plurality of groups by a signal on a group request terminal of the second address generator. In one embodiment the storage elements are part of a dualport random-access-memory (RAM), and are accessed by each of the first and second address generators using a number of pairs of pointer registers that are coupled to the address generators. Each pair of pointer registers includes a read pointer register that indicates a corresponding group's next storage element to be read and a write pointer register that indicates the group's next storage element to be written.
Inventors
- 👤 Larry N. Wakeman
- 👤 Roy T. Myers, Jr.
- 👤 Wesley C. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:04
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/065
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
290 words
A multi-first-in-first-out memory circuit comprising: a memory comprising a plurality of first address terminals, a plurality of first data terminals, a plurality of second address terminals, a plurality of second data terminals and a plurality of groups, each group comprising a plurality of storage elements; wherein said memory can supply data signals on said first data terminals driven by data values stored in a storage element identified by first address signals received on said first address terminals, and said memory can supply data signals on said second data terminals driven by data values stored in a storage element identified by second address signals received on said second address terminals; further wherein said memory can use data signals received on said first data terminals to store data values in a storage element identified by first address signals received on said first address terminals, and said memory can use data signals received on said second data terminals to store data values in a storage element identified by second address signals received on said second address terminals; a first address generator comprising a first address bus and a sequencer, said first address bus being coupled to said first address terminals; wherein said sequencer allows said first address generator to supply first address signals of a storage element from each of said groups, said each group being successively selected by said sequencer from said plurality of groups; and a second address generator comprising a second address bus and a group request terminal, said second address bus being coupled to said second address terminals; wherein said second address generator supplies second address signals of successive storage elements from a second group, said second group being identified by a request signal on said group request terminal.
Claim 2
Dependent Claim
290 words
A multi-first-in-first-out memory circuit comprising: a memory comprising a plurality of first address terminals, a plurality of first data terminals, a plurality of second address terminals, a plurality of second data terminals and a plurality of groups, each group comprising a plurality of storage elements; wherein said memory can supply data signals on said first data terminals driven by data values stored in a storage element identified by first address signals received on said first address terminals, and said memory can supply data signals on said second data terminals driven by data values stored in a storage element identified by second address signals received on said second address terminals; further wherein said memory can use data signals received on said first data terminals to store data values in a storage element identified by first address signals received on said first address terminals, and said memory can use data signals received on said second data terminals to store data values in a storage element identified by second address signals received on said second address terminals; a first address generator comprising a first address bus and a sequencer, said first address bus being coupled to said first address terminals; wherein said sequencer allows said first address generator to supply first address signals of a storage element from each of said groups, said each group being successively selected by said sequencer from said plurality of groups; and a second address generator comprising a second address bus and a group request terminal, said second address bus being coupled to said second address terminals; wherein said second address generator supplies second address signals of successive storage elements from a second group, said second group being identified by a request signal on said group request terminal.
Claim 3
Dependent Claim
109 words
The multi-first-in-first-out memory circuit of claim 1 further comprising: a plurality of pairs of pointer registers, each pair corresponding to one of said groups, a first pointer register of each pair being coupled to said first address generator and a second pointer register of each pair being coupled to said second address generator; wherein said first address generator uses a value encoded in a first pointer register to generate said first address signals and updates said value after said use; and further wherein said second address generator uses a value encoded in a second pointer register to generate said second address signals and updates said value after said use.
Claim 4
Dependent Claim
153 words
The multi-first-in-first-out memory circuit of claim 1 further comprising: a plurality of read pointer registers, each read pointer register corresponding to one of said groups; a plurality of write pointer registers, each write pointer register corresponding to one of said groups; wherein a read pointer register corresponding to a group is coupled to one of said first address generator and said second address generator and a write pointer register corresponding to said group is coupled to the other of said first address generator and said second address generator; and further wherein for each group said first address generator uses a value encoded in one of said read pointer register and said write pointer register to generate said first address signals and said second address generator uses a value encoded in the other of said read pointer register and said write pointer register of one of said groups to generate said second address signals.
Claim 5
Dependent Claim
68 words
The multi-first-in-first-out memory circuit of claim 1, wherein half of said groups are receive groups and the other half are transmit groups, each group comprising an equal number of storage elements; wherein said first group is selected cyclically from said plurality of receive and transmit groups; and further wherein said second group is selected from said plurality of receive and transmit groups in response to said request signal.
Claim 6
Dependent Claim
66 words
The multi-first-in-first-out memory circuit of claim 1 further comprising: a plurality of counter registers, each of said counter registers corresponding to one of said groups; wherein one of said address generators increments a value encoded in a counter register when a data value is stored in a storage element of a group corresponding to said counter register and stores said incremented value in said counter register.
Claim 7
Dependent Claim
66 words
The multi-first-in-first-out memory circuit of claim 1 further comprising: a plurality of counter registers, each of said counter registers corresponding to one of said groups; wherein one of said address generators decrements a value encoded in a counter register when a data value is supplied from a storage element of a group corresponding to said counter register and stores said decremented value in said counter register.
Claim 8
Dependent Claim
75 words
The multi-first-in-first-out memory circuit of claim 1 further comprising: a plurality of counter registers, each of said counter registers corresponding to one of said groups; wherein neither of said address generators changes a value encoded in a counter register when during a common time period: a data value is supplied from a storage element of a group corresponding to said counter register; and a data value is stored in a storage element of said group.
Claim 9
Independent Claim
67 words
A method for accessing storage locations in a random-access-memory, said method comprising: supplying first address signals of a storage location located in a first group of a plurality of groups of storage locations, said first group being successively selected from said plurality of groups; and supplying second address signals of successive storage elements located in a second group, said second group being identified by a request signal.
Claim 10
Independent Claim
67 words
A method for accessing storage locations in a random-access-memory, said method comprising: supplying first address signals of a storage location located in a first group of a plurality of groups of storage locations, said first group being successively selected from said plurality of groups; and supplying second address signals of successive storage elements located in a second group, said second group being identified by a request signal.
Claim 11
Dependent Claim
60 words
A method for accessing storage locations as recited in claim 8, the method further comprising: using a value encoded in a first pointer register to generate said first address signals and updating said value after said use; and using a value encoded in a second pointer register to generate said second address signals and updating said value after said use.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |