US5594445A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pipelined analog to digital converters and interstage amplifiers for such converters
Assignee: NXP BV
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Filing: 1993-11-02
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Granted: 1997-01-14
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Expires: 2013-11-02
Abstract
Abstract An interstage amplifier for a pipelined analog to digital converter comprises an operational amplifier (50) having a first pair of capacitors (55,58), a second pair of capacitors (56,57), and switching means (59-62) connected to the capacitors and amplifier. The switching means interchanges the capacitor connections to compensate for offset in the amplifier. The arrangement provides first-order correction of capacitor mismatch.
Inventors
- 👤 Bernard Ginetti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:40
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0675; H03M1/0678; H03M1/068; H03M1/0682; H03M1/12; H03M1/14; H03M1/16; H03M1/164; H03M1/167; H03M1/168; H03M1/34; H03M1/38; H03M1/44; H03M1/442
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
198 words
An interstage amplifier for a pipelined analog to digital converter, comprising an operational amplifier (50) having balanced amplifying paths; a first pair of capacitors (55,58); a second pair of capacitors (56,57); and switching (59-66) means connected to the capacitors and said amplifier and for: (i) during a first phase, enabling said first pair of capacitors to receive a respective first sample of a first signal; (ii) during a second phase, enabling said second pair of capacitors to receive a second sample of the first signal; (iii) during a third phase, enabling said first pair of capacitors to receive a first sample of a second or reference signal and to enable charge to be transferred from each of said first pair of capacitors by way of a respective path of the amplifier to a respective one of said second pair of capacitors; and (iv) during a fourth phase, enabling said second pair of capacitors to receive a second sample of said second or reference signal and to enable charge to be transferred from each of said second pair of capacitors by way of a respective path of the amplifier to the respective one of said first pair of capacitors.
Claim 2
Dependent Claim
198 words
An interstage amplifier for a pipelined analog to digital converter, comprising an operational amplifier (50) having balanced amplifying paths; a first pair of capacitors (55,58); a second pair of capacitors (56,57); and switching (59-66) means connected to the capacitors and said amplifier and for: (i) during a first phase, enabling said first pair of capacitors to receive a respective first sample of a first signal; (ii) during a second phase, enabling said second pair of capacitors to receive a second sample of the first signal; (iii) during a third phase, enabling said first pair of capacitors to receive a first sample of a second or reference signal and to enable charge to be transferred from each of said first pair of capacitors by way of a respective path of the amplifier to a respective one of said second pair of capacitors; and (iv) during a fourth phase, enabling said second pair of capacitors to receive a second sample of said second or reference signal and to enable charge to be transferred from each of said second pair of capacitors by way of a respective path of the amplifier to the respective one of said first pair of capacitors.
Claim 3
Dependent Claim
30 words
An interstage amplifier according to claim 1, wherein the switching means (59-66) is arranged for interchanging inputs for said paths and interchanging outputs from said paths during said fourth phase.
Claim 4
Dependent Claim
61 words
A pipelined analog-to-digital converter having a multiplicity of stages and including at least one interstage amplifier according to claim 1 or 2, said converter including one stage which is connected by said switching means to provide an output signal as said first signal to said amplifier and means for providing a signed reference signal to said amplifier as said second signal.
Claim 5
Dependent Claim
136 words
A pipelined analog-to-digital converter according to claim 3, and further comprising: a third pair of capacitors (155,158); a fourth pair of capacitors (156,157) and switching means (159-166) for enabling during said third and fourth phases said third and fourth pair of capacitors to receive a first and a second sample respectively of an output signal of a second stage adjacent said one stage of the converter and for enabling during said first and second phases said third and fourth pairs of capacitors to receive samples of a reference signal and to transfer charge between corresponding capacitors of said third and fourth pairs thereof in a manner corresponding to the enabling of said first and second pairs of capacitors during said third and fourth phases, whereby said operational amplifier constitutes two successive interstage amplifiers for the converter.
Claim 6
Independent Claim
135 words
A method for interstage amplification in a pipelined analog to digital converter having a multiplicity of stages and at least one interstage amplifier which includes a first pair of capacitors (55,58) and a second pair of capacitors (56,57), the method comprising: feeding to said first and second pairs of capacitors respective samples of the output of a stage of the converter and respective samples of a reference signal; transferring charge from each capacitor of said first pair to a respective capacitor of the second pair while the capacitors of said first pair are receiving their respective samples of the reference signal; and transferring charge from each capacitor of said second pair to a respective capacitor of said first pair while the capacitors of said second pair are receiving their respective samples of the reference signal.
Claim 7
Independent Claim
135 words
A method for interstage amplification in a pipelined analog to digital converter having a multiplicity of stages and at least one interstage amplifier which includes a first pair of capacitors (55,58) and a second pair of capacitors (56,57), the method comprising: feeding to said first and second pairs of capacitors respective samples of the output of a stage of the converter and respective samples of a reference signal; transferring charge from each capacitor of said first pair to a respective capacitor of the second pair while the capacitors of said first pair are receiving their respective samples of the reference signal; and transferring charge from each capacitor of said second pair to a respective capacitor of said first pair while the capacitors of said second pair are receiving their respective samples of the reference signal.
Claim 8
Dependent Claim
34 words
A method according to claim 5 wherein said transferring of charge is made by way of respective paths of a differential operational amplifier, the method further comprising interchanging said paths between successive charge transfers.
Claim 9
Dependent Claim
36 words
A method according to claim 5 wherein said feeding is performed during a first phase in respect of said first pair of capacitors and during a second phase in respect of said second pair of capacitors.
Claim 10
Dependent Claim
42 words
A method according to claim 7 wherein said transferring of charge from each capacitor of said first pair is performed during a third phase and said transferring of charge from each capacitor of said second pair is performed during a fourth phase.
References Cited (Backward Citations)
US5047772A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |