US5594442A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Configuration programming of a digital audio serial port using no additional pins
Assignee: Cirrus Logic Inc
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Filing: 1994-03-15
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Granted: 1997-01-14
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Expires: 2014-03-15
Abstract
Abstract A stereo digital-to-analog converter is able to operate in an 8 pin package yet to operate under a variety of serial data input formats. The normal de-emphasis pin can be used for receiving a static de-emphasis signal, an external serial clock, or programming data for the serial data formats. In addition metal and wire bond options are used to provide more flexibility in the manufacturing process.
Inventors
- 👤 John J. Paulos
- 👤 Gautham D. Kamath
- 👤 Andrew W. Krone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:15
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/39; H03M3/392; H03M3/458; H03M3/50
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
94 words
A delta-sigma digital-to-analog converter having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, together with a pin for receiving a master clock signal, and providing left and right channels of analog signal, wherein said serial data clock can be generated inside said digital-to-analog converter by dividing said master clock signal, and wherein said serial data clock terminal is able to receive data for setting one or more of the functions selected from the group of serial data format, test mode, and de-emphasis selection.
Claim 2
Dependent Claim
94 words
A delta-sigma digital-to-analog converter having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, together with a pin for receiving a master clock signal, and providing left and right channels of analog signal, wherein said serial data clock can be generated inside said digital-to-analog converter by dividing said master clock signal, and wherein said serial data clock terminal is able to receive data for setting one or more of the functions selected from the group of serial data format, test mode, and de-emphasis selection.
Claim 3
Dependent Claim
52 words
A digital-to-analog converter having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, the improvement comprising having at least one pin of said three-wire serial interface which is able to receive and differentiate between one or more of a plurality of functions.
Claim 4
Dependent Claim
52 words
A digital-to-analog converter having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, the improvement comprising having at least one pin of said three-wire serial interface which is able to receive and differentiate between one or more of a plurality of functions.
Claim 5
Dependent Claim
66 words
The digital-to-analog converter set forth in claim 2 wherein said digital-to-analog converter receives an additional signal of a masterclock and wherein said serial data clock is generated inside said digital-to-analog converter by dividing said masterclock signal, and wherein said serial data clock terminal receives data for setting one or more of the functions selected from the group of serial data format, test mode, and de-emphasis selection.
Claim 6
Dependent Claim
51 words
The digital-to-analog converter set forth in claim 2 wherein said serial data clock terminal is able to receive and decode one of either serial data format information or test mode function information in the time interval between power up and normal operation, and an external serial data clock during normal operation.
Claim 7
Dependent Claim
54 words
The digital-to-analog converter set forth in claim 2 which includes an additional input terminal wherein said digital-to-analog converter recognizes a data sequence on said additional input terminal as one or more of the group consisting of programming data and test data, and recognizes a persistent logic level as data which is not programming data.
Claim 8
Dependent Claim
46 words
The digital-to-analog converter set forth in claim 2 wherein a wire bonding option is used to connect one of a plurality of bonding pads to an input terminal of said digital-to-analog converter, wherein each of said plurality of bonding pads provides different default serial data format.
Claim 9
Dependent Claim
30 words
The digital-to-analog converter set forth in claim 6 wherein at least one pin is able to receive and decode serial data format information which overrides said default serial data format.
Claim 10
Dependent Claim
48 words
The digital-to-analog converter set forth in claim 3 wherein said serial data format includes a predetermined preamble followed by a predetermined number of data bits, said predetermined preamble having at least one logic 0 to logic 1 transition and at least one logic 1 to logic 0 transition.
Claim 11
Dependent Claim
54 words
The digital-to-analog converter set forth in claim 8 wherein said serial data format is ignored by said digital-to-analog converter if said predetermined number of data bits are all of the same logic state such that the preamble bits plus the data bits contain only one logic 0 bit or only one logic 1 bit.
Claim 12
Dependent Claim
37 words
The digital-to-analog converter set forth in claim 9 wherein said preamble is a logic 010 sequence, and wherein said serial data is ignored by said digital-to-analog converter if said predetermined number of data bits are logic 0.
Claim 13
Dependent Claim
48 words
The digital-to-analog converter set forth in claim 4 wherein said serial data format includes a predetermined preamble followed by a predetermined number of data bits, said predetermined preamble having at least one logic 0 to logic 1 transition and at least one logic 1 to logic 0 transition.
Claim 14
Dependent Claim
54 words
The digital-to-analog converter set forth in claim 11 wherein said serial data format is ignored by said digital-to-analog converter if said predetermined number of data bits are all of the same logic state such that the preamble bits plus the data bits contain only one logic 0 bit or only one logic 1 bit.
Claim 15
Dependent Claim
37 words
The digital-to-analog converter set forth in claim 12 wherein said preamble is a logic 010 sequence, and wherein said serial data is ignored by said digital-to-analog converter if said predetermined number of data bits are logic 0.
Claim 16
Dependent Claim
48 words
The digital-to-analog converter set forth in claim 5 wherein said serial data format includes a predetermined preamble followed by a predetermined number of data bits, said predetermined preamble having at least one logic 0 to logic 1 transition and at least one logic 1 to logic 0 transition.
Claim 17
Dependent Claim
54 words
The digital-to-analog converter set forth in claim 14 wherein said serial data format is ignored by said digital-to-analog converter if said predetermined number of data bits are all of the same logic state such that the preamble bits plus the data bits contain only one logic 0 bit or only one logic 1 bit.
Claim 18
Dependent Claim
37 words
The digital-to-analog converter set forth in claim 15 wherein said preamble is a logic 010 sequence, and wherein said serial data is ignored by said digital-to-analog converter if said predetermined number of data bits are logic 0.
Claim 19
Dependent Claim
52 words
An analog-to-digital converter having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, the improvement comprising having at least one pin of said three-wire serial interface which is able to receive and differentiate between one or more of a plurality of functions.
Claim 20
Dependent Claim
52 words
An analog-to-digital converter having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, the improvement comprising having at least one pin of said three-wire serial interface which is able to receive and differentiate between one or more of a plurality of functions.
Claim 21
Dependent Claim
62 words
The analog-to-digital converter set forth in claim 17 wherein said analog-to-digital converter receives an additional signal of a masterclock and wherein said serial data clock is generated inside said analog-to-digital converter by dividing said masterclock signal, and wherein said serial data clock terminal receives data for setting one of the functions selected from the group of serial data format and test mode.
Claim 22
Dependent Claim
54 words
The analog-to-digital converter set forth in claim 17 wherein said serial data clock terminal is able to receive and decode one of either serial data format information or test mode function information in the time interval between power up and normal operation, and to transmit or receive a serial data clock during normal operation.
Claim 23
Dependent Claim
54 words
The analog-to-digital converter set forth in claim 17 which includes an additional input terminal wherein said analog-to-digital converter recognizes a data sequence on said additional input terminal as one or more of the group consisting of programming data and test data, and recognizes a persistent logic level as data which is not programming data.
Claim 24
Dependent Claim
46 words
The analog-to-digital converter set forth in claim 17 wherein a wire bonding option is used to connect one of a plurality of bonding pads to an input terminal of said analog-to-digital converter, wherein each of said plurality of bonding pads provides different default serial data format.
Claim 25
Dependent Claim
30 words
The analog-to-digital converter set forth in claim 21 wherein at least one pin is able to receive and decode serial data format information which overrides said default serial data format.
Claim 26
Dependent Claim
48 words
The analog-to-digital converter set forth in claim 18 wherein said serial data format includes a predetermined preamble followed by a predetermined number of data bits, said predetermined preamble having at least one logic 0 to logic 1 transition and at least one logic 1 to logic 0 transition.
Claim 27
Dependent Claim
49 words
The digital-to-analog converter set forth in claim 23 wherein said serial data format is ignored by said digital-to-analog converter if said predetermined number of data bits are all of the same logic state such that the preamble plus the data bits contain only one logic 0 or logic 1.
Claim 28
Dependent Claim
37 words
The analog-to-digital converter set forth in claim 24 wherein said preamble is a logic 010 sequence, and wherein said serial data is ignored by said analog-to-digital converter if said predetermined number of data bits are logic 0.
Claim 29
Dependent Claim
48 words
The analog-to-digital converter set forth in claim 19 wherein said serial data format includes a predetermined preamble followed by a predetermined number of data bits, said predetermined preamble having at least one logic 0 to logic 1 transition and at least one logic 1 to logic 0 transition.
Claim 30
Dependent Claim
49 words
The digital-to-analog converter set forth in claim 26 wherein said serial data format is ignored by said digital-to-analog converter if said predetermined number of data bits are all of the same logic state such that the preamble plus the data bits contain only one logic 0 or logic 1.
Claim 31
Dependent Claim
37 words
The analog-to-digital converter set forth in claim 27 wherein said preamble is a logic 010 sequence, and wherein said serial data is ignored by said analog-to-digital converter if said predetermined number of data bits are logic 0.
Claim 32
Dependent Claim
48 words
The analog-to-digital converter set forth in claim 20 wherein said serial data format includes a predetermined preamble followed by a predetermined number of data bits, said predetermined preamble having at least one logic 0 to logic 1 transition and at least one logic 1 to logic 0 transition.
Claim 33
Dependent Claim
49 words
The digital-to-analog converter set forth in claim 29 wherein said serial data format is ignored by said digital-to-analog converter if said predetermined number of data bits are all of the same logic state such that the preamble plus the data bits contain only one logic 0 or logic 1.
Claim 34
Dependent Claim
37 words
The analog-to-digital converter set forth in claim 30 wherein said preamble is a logic 010 sequence, and wherein said serial data is ignored by said analog-to-digital converter if said predetermined number of data bits are logic 0.
Claim 35
Dependent Claim
93 words
A delta-sigma analog-to-digital converter having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, together with a pin for receiving a master clock signal, and providing left and right channels .of analog signal, wherein said serial data clock can be generated inside said analog-to-digital converter by dividing said masterclock signal, and wherein said serial data clock terminal is able to receive data for setting one or more of the functions selected from the group of serial data format, test mode, and de-emphasis selection.
Claim 36
Dependent Claim
93 words
A delta-sigma analog-to-digital converter having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, together with a pin for receiving a master clock signal, and providing left and right channels .of analog signal, wherein said serial data clock can be generated inside said analog-to-digital converter by dividing said masterclock signal, and wherein said serial data clock terminal is able to receive data for setting one or more of the functions selected from the group of serial data format, test mode, and de-emphasis selection.
Claim 37
Dependent Claim
53 words
A data conversion device having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, the improvement comprising having at least one pin of said three-wire serial interface which is able to receive and differentiate between one or more of a plurality of functions.
Claim 38
Dependent Claim
53 words
A data conversion device having a three-wire serial interface comprising a serial data terminal, a serial data clock terminal, and a left/right clock terminal, the improvement comprising having at least one pin of said three-wire serial interface which is able to receive and differentiate between one or more of a plurality of functions.
Claim 39
Dependent Claim
59 words
The data conversion device set forth in claim 33 wherein said data conversion device receives an additional signal of a masterclock and wherein said serial data clock is generated inside said data conversion device by dividing said masterclock signal, and wherein said serial data clock terminal receives data for setting the serial data format in said data conversion device.
References Cited (Backward Citations)
US5436943A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |