Semiconductor apparatus having wiring structure of an integrated circuit in which a plurality of logic circuits of the same structure are arranged in the same direction

Claim 2

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with said first metal wiring.

Claim 3

The semiconductor apparatus of claim 1, wherein said second metal wiring is connected at one end to a substantially middle point of said first metal wiring.

Claim 4

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with the first metal wiring, wherein said first metal wiring includes a plurality of wirings each corresponding to a predetermined number of said logic circuits of said first circuit and each connected to one of the input terminals of each of said logic circuits of said predetermined number of said logic circuits, and wherein said second metal wiring is connected to a predetermined point of each of the plurality of wirings of said first metal wiring.

Claim 5

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with the first metal wiring, wherein said first metal wiring includes a plurality of wirings each corresponding to a predetermined number of said logic circuits of said first circuit and each connected to one of the input terminals of each of said logic circuits of said predetermined number of said logic circuits, and wherein said second metal wiring is connected to a predetermined point of each of the plurality of wirings of said first metal wiring.

Claim 6

The semiconductor apparatus of claim 3, wherein said second metal wiring is connected to a substantially middle point of each of the plurality of wirings of said first metal wiring.

Claim 7

The semiconductor apparatus of claim 1, wherein said first circuit includes n of said logic circuits and said second metal wiring is connected at one end to a point between an (n/2)th logic circuit and an (n/2)+1-th logic circuit.

Claim 8

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits and having a first signal propagation delay per unit length; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit including a logic circuit closest to said output terminal and a logic circuit farthest from said output terminal; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with said first metal wiring and having a second signal propagation delay per unit length less than said first signal propagation delay per unit length, so that a difference in signal propagation delay between said closest logic circuit and said farthest logic circuit decreases and a signal propagation speed in general increases relative to a situation where said second metal wiring does not have said portion extending substantially parallel to and partially overlapping with said first metal wiring.

Claim 9

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits and having a first signal propagation delay per unit length; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit including a logic circuit closest to said output terminal and a logic circuit farthest from said output terminal; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with said first metal wiring and having a second signal propagation delay per unit length less than said first signal propagation delay per unit length, so that a difference in signal propagation delay between said closest logic circuit and said farthest logic circuit decreases and a signal propagation speed in general increases relative to a situation where said second metal wiring does not have said portion extending substantially parallel to and partially overlapping with said first metal wiring.

Claim 10

The semiconductor apparatus of claim 6, wherein said second metal wiring is connected at one end to a substantially middle point of said first metal wiring.

Claim 11

The semiconductor apparatus of claim 6, wherein said first circuit includes n of said logic circuits and said second metal wiring is connected at one end to a point between an (n/2)th logic circuit and an (n/2)+1-th logic circuit.

Claim 12

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits and having a first signal propagation delay per unit length; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit including a logic circuit closest to said output terminal and a logic circuit farthest from said output terminal; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with the first metal wiring and having a second signal propagation delay per unit length less than said first signal propagation delay per unit length, wherein said first metal wiring includes a plurality of wirings each corresponding to a predetermined number of said logic circuits of said first circuit and each connected to one of the input terminals of each of said logic circuits of said predetermined number of said logic circuits, and wherein said second metal wiring is connected to a predetermined point of each of the plurality of wirings of said first metal wiring, so that a difference in signal propagation delay between said closest logic circuit and said farthest logic circuit decreases and a signal propagation speed in general increases relative to a situation where said second metal wiring does not have said portion extending substantially parallel to and partially overlapping with said first metal wiring.

Claim 13

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits and having a first signal propagation delay per unit length; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit including a logic circuit closest to said output terminal and a logic circuit farthest from said output terminal; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with the first metal wiring and having a second signal propagation delay per unit length less than said first signal propagation delay per unit length, wherein said first metal wiring includes a plurality of wirings each corresponding to a predetermined number of said logic circuits of said first circuit and each connected to one of the input terminals of each of said logic circuits of said predetermined number of said logic circuits, and wherein said second metal wiring is connected to a predetermined point of each of the plurality of wirings of said first metal wiring, so that a difference in signal propagation delay between said closest logic circuit and said farthest logic circuit decreases and a signal propagation speed in general increases relative to a situation where said second metal wiring does not have said portion extending substantially parallel to and partially overlapping with said first metal wiring.

Claim 14

The semiconductor apparatus of claim 9, wherein said second metal wiring is connected to a substantially middle point of each of the plurality of wirings of said first metal wiring.

Claim 15

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of groups of logic circuits of an identical structure, said groups of logic circuits including a predetermined number of said logic circuits each having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said groups of logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits and having a first signal propagation delay per unit length; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the groups of logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit including a logic circuit closest to said output terminal and a logic circuit farthest from said output terminal; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with the first metal wiring and having a second signal propagation delay per unit length less than said first signal propagation delay per unit length, so that a difference in signal propagation delay between said closest logic circuit and said farthest logic circuit decreases and a signal propagation speed in general increases relative to a situation where said second metal wiring does not have said portion extending substantially parallel to and partially overlapping with said first metal wiring.

Claim 16

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of groups of logic circuits of an identical structure, said groups of logic circuits including a predetermined number of said logic circuits each having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said groups of logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits and having a first signal propagation delay per unit length; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the groups of logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit including a logic circuit closest to said output terminal and a logic circuit farthest from said output terminal; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with the first metal wiring and having a second signal propagation delay per unit length less than said first signal propagation delay per unit length, so that a difference in signal propagation delay between said closest logic circuit and said farthest logic circuit decreases and a signal propagation speed in general increases relative to a situation where said second metal wiring does not have said portion extending substantially parallel to and partially overlapping with said first metal wiring.

Claim 17

The semiconductor apparatus of claim 11, wherein said second metal wiring is connected to a substantially middle point of said first metal wiring.

Claim 18

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with the first metal wiring, wherein said first metal wiring includes a plurality of wirings each corresponding to a predetermined number of said logic circuits of said first circuit and each connected to one of the input terminals of each of said logic circuits of said predetermined number of said logic circuits, wherein said second metal wiring includes a plurality of wirings, and wherein said second metal wiring is connected to a predetermined point of each of the plurality of wirings of said first metal wiring.

Claim 19

A semiconductor apparatus comprising: a semiconductor substrate; a first circuit arranged on a major surface of said semiconductor substrate and including a plurality of logic circuits of an identical structure, said logic circuits having input terminals supplied with identical signals; first metal wiring arranged on said semiconductor substrate in a direction substantially identical to a direction of arrangement of said logic circuits, said first metal wiring connected to one of the input terminals of each of the logic circuits; a second circuit arranged on the major surface of said semiconductor substrate in an outside area which does not overlap an area extending in a direction substantially perpendicular to the direction of arrangement of the logic circuits, said second circuit having an output terminal supplying an identical signal to said one of the input terminals of each of the logic circuits of said first circuit; and second metal wiring connected between said output terminal of said second circuit and said first metal wiring and having a portion extending substantially parallel to and partially overlapping with the first metal wiring, wherein said first metal wiring includes a plurality of wirings each corresponding to a predetermined number of said logic circuits of said first circuit and each connected to one of the input terminals of each of said logic circuits of said predetermined number of said logic circuits, wherein said second metal wiring includes a plurality of wirings, and wherein said second metal wiring is connected to a predetermined point of each of the plurality of wirings of said first metal wiring.

Claim 20

The semiconductor apparatus of claim 13, wherein said second metal wiring is connected to a substantially middle point of each of the plurality of wirings of said first metal wiring.

Claim 21

The semiconductor apparatus of claim 13, wherein said first circuit includes n of said logic circuits and said second metal wiring is connected to a point between an (n/2)th logic circuit and an (n/2)+1-th logic circuit.

Claim 22

The semiconductor apparatus of claim 13, wherein said plurality of wirings of said second metal wiring includes an interconnecting wiring connected to said predetermined point of each of the plurality of wirings of said first metal wiring, and an output wiring connected between said output terminal and a predetermined point of said interconnecting wiring.

Claim 23

The semiconductor apparatus of claim 16, wherein said interconnecting wiring has a portion extending substantially parallel to and partially overlapping with the first metal wiring.

Claim 24

The semiconductor apparatus of claim 16, wherein said output wiring has a portion extending substantially parallel to and partially overlapping with the first metal wiring.

Claim 25

The semiconductor apparatus of claim 16, wherein said predetermined point of said interconnecting wiring is a substantially middle point of said interconnecting wiring.

Claim 26

The semiconductor apparatus of claim 17, wherein said portion of said interconnecting wiring includes a plurality of portions each extending substantially parallel to and partially overlapping with each of the plurality of wirings of the first metal wiring, respectively.

Claim 27

The semiconductor apparatus of claim 17, wherein said portion of said interconnecting wiring extends substantially parallel to and partially overlaps with a portion of said output wiring.