Video game card having interrupt resistant behavior

Claim 2

A video game card for interfacing a game controller having one or more analog input devices to a personal computer including a microprocessor having digital data and control buses and a card slot for receiving I/O cards, the game card comprising: a circuit board for mounting electrical components and connectors thereupon, the circuit board sized to fit in the card slot of the personal computer; a game card connector for receiving an analog signal from the game controller, the analog signal having a signal level corresponding to a state of a corresponding game controller input device; a bus connector for connecting the circuit board to the computer data and control bus; and a game card circuit for providing to the microprocessor a digital signal corresponding to the analog signal level, the circuit including means for asserting the digital signal responsive to a "write" to the game card by the personal computer microprocessor and means for deasserting the digital signal responsive to a number of "reads" sent to the game card by the personal computer, the "read" at which the digital signal is deasserted being determined from the analog signal level.

Claim 3

A video game card according to claim 1 wherein the circuit includes: means for converting the analog signal to a binary count; and means for counting the number of "reads" sent to the game card by the personal computer microprocessor; the means for deasserting the digital signal being operative to deassert said signal when the number of "reads" is equal to or greater than the binary count.

Claim 4

A video game card according to claim 2 wherein the converting means includes an analog to digital converter.

Claim 5

A video game card according to claim 3 wherein the converting means includes a resistance to voltage circuit interposed between the analog signal and the analog to digital converter for receiving the analog signal and converting the analog signal to an analog voltage signal.

Claim 6

A video game card according to claim 2 wherein the circuit includes a means for storing the binary count.

Claim 7

A video game card according to claim 2 wherein the deasserting means includes a comparator for comparing the binary count to the number of "reads."

Claim 8

A video game card according to claim 1 wherein the game card connector receives a plurality of said analog signals from the game controller, each analog signal having a signal level corresponding to the state of a corresponding game controller input device; the game card further comprising one of said game card circuits for each analog signal.

Claim 9

A video game card according to claim 7 wherein the game card circuits comprise: a plurality of latches, each latch storing a binary count corresponding to each analog signal level; means for counting the number of "reads" sent to the game card by the personal computer microprocessor; and a plurality of comparators having first and second inputs and an output, the first input of each comparator being coupled to the counting means and the second input of each comparator being coupled to a corresponding latch for comparing the counter count to the binary count of the corresponding latch, the output of each comparator indicating the result of the comparison.

Claim 10

A video game card according to claim 8 wherein the game card circuit includes a means for providing the comparator outputs to the personal computer microprocessor responsive to a "read" sent to the game card by the microprocessor.

Claim 11

A video game card according to claim 1 wherein the circuit for providing a digital signal to the microprocessor corresponding to the analog signal level includes: means for establishing a ramp voltage, the ramp voltage being increased responsive to a "read" by the personal computer microprocessor; and means for comparing the ramp voltage to the analog signal level, the comparing means asserting the digital signal when the ramp voltage is equal to or greater than the analog signal level and deasserting the digital signal when the ramp voltage is less than the analog signal level.

Claim 12

A video game card according to claim 10 wherein the means for establishing a ramp voltage includes: a counter for counting the number of reads by the personal computer microprocessor; and a voltage generator coupled to the counter, the voltage generator generating a ramp voltage proportional to the counter count.

Claim 13

A video game card according to claim 11 wherein the means for comparing the ramp voltage to the analog signal level includes: a comparator having a first input coupled to the voltage generator for receiving the ramp voltage, a second input coupled to the game card connector for receiving the analog signal from the game controller, and an output for producing the digital signal; and a current sink coupled to the second input.

Claim 14

A video game card according to claim 12 wherein the comparator includes: an operational amplifier having a first input, a second input, and an output; and an impedance network coupled to the operational amplifier.

Claim 17

A method of signalling to a digital personal computer the state of a controller input device according to claim 14 wherein the step of sampling the analog signal includes converting the analog signal to an analog voltage signal.

Claim 18

A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of converting the sample to a binary count includes storing the binary count.

Claim 19

A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of counting the number of "reads" since the "write" includes incrementing a counter responsive to each detected "read."

Claim 20

A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of asserting the digital signal responsive to the detected "write" includes setting a flip-flop to an asserted state.

Claim 21

A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of deasserting the digital signal when the number of "reads" is equal to the binary count includes setting a flip-flop to a deasserted state.

Claim 22

A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of detecting a "write" sent by the personal computer to the game card includes: assigning a game card address to the game card; comparing an address received from the personal computer with the assigned game card address; and detecting a "write" when the received address is equal to the game card address.

Claim 23

A method of signalling to a digital personal computer the state of a controller input device according to claim 20 wherein the step of assigning a game card address to the game board includes selecting one of a plurality of game card addresses.

Claim 24

A method of signalling to a digital personal computer the state of a controller input device according to claim 15 further including repeating each step for a plurality of analog signals corresponding to a plurality of controller input devices.

Claim 25

A video game/simulation system for simulating operation of a complex system having a plurality of user-controlled functions, the system comprising: a computer having a microprocessor operable under control of a video game/simulation program, a display for displaying images produced by the program, and an input/output bus for connecting peripheral input and output devices to the microprocessor by producing a peripheral address and exchanging data therewith; a video game/simulator controller having a plurality of input devices, each input device having an analog signal line for transmitting an analog signal corresponding to the state of the input device; an interrupt resistant game card coupled to the input/output bus and having a game card connector coupled to the analog signal lines for receiving the corresponding analog signals from the video game/simulator controller, the game card having means for converting each analog signal to a corresponding digital signal, and means for asserting the digital signals responsive to a "write" sent to the game card by the computer microprocessor and deasserting the digital signals responsive to a number of "reads" sent to the game card by the computer, the "read" at which a digital signal is deasserted being determined by a level of the corresponding analog signal; means in the computer for writing to the game card; means in the computer for reading from the game card to receive the plurality of digital signals corresponding to the plurality of input devices of the video game/simulator controller; and means for effecting a corresponding change in the displayed images produced by the program responsive to the received digital signals.

Claim 26

A video game/simulation system for simulating operation of a complex system having a plurality of user-controlled functions, the system comprising: a computer having a microprocessor operable under control of a video game/simulation program, a display for displaying images produced by the program, and an input/output bus for connecting peripheral input and output devices to the microprocessor by producing a peripheral address and exchanging data therewith; a video game/simulator controller having a plurality of input devices, each input device having an analog signal line for transmitting an analog signal corresponding to the state of the input device; an interrupt resistant game card coupled to the input/output bus and having a game card connector coupled to the analog signal lines for receiving the corresponding analog signals from the video game/simulator controller, the game card having means for converting each analog signal to a corresponding digital signal, and means for asserting the digital signals responsive to a "write" sent to the game card by the computer microprocessor and deasserting the digital signals responsive to a number of "reads" sent to the game card by the computer, the "read" at which a digital signal is deasserted being determined by a level of the corresponding analog signal; means in the computer for writing to the game card; means in the computer for reading from the game card to receive the plurality of digital signals corresponding to the plurality of input devices of the video game/simulator controller; and means for effecting a corresponding change in the displayed images produced by the program responsive to the received digital signals.

Claim 27

A video game/simulation system according to claim 23 wherein the means for converting the analog signals to corresponding digital signals includes, for each analog signal: means for asserting the corresponding digital signal responsive to the "write" sent to the game card by the computer microprocessor; means for converting the analog signal to a binary count; means for counting the number of "reads" sent to the game card by the computer microprocessor; and means for deasserting the digital signal when the number of "reads" is equal to or greater than the binary count.

Claim 28

A video game/simulation system according to claim 23 wherein the means for converting the plurality of analog signals to a corresponding plurality of digital signals includes: means for establishing a ramp voltage, the ramp voltage being increased responsive to a "read" by the computer microprocessor; and means for comparing the ramp voltage to the analog signal level, the comparing means asserting the digital signal when the ramp voltage is equal to or greater than the analog signal level and deasserting the digital signal when the ramp voltage is less than the analog signal level.

Claim 29

A video game/simulation system according to claim 23 wherein the interrupt resistant game card includes: a first connector coupled to the analog signal lines of the input device for receiving the corresponding plurality of analog signals from the controller; and a second connector for receiving a plurality of analog signals from a second controller.

Claim 30

A video game card for interfacing a game controller having one or more input devices to a computer including a microprocessor having data and control buses and a card slot for receiving I/O cards, the game card comprising: a circuit board for mounting electrical components and connectors thereupon, the circuit board sized to fit in the card slot of the personal computer; a game card connector for receiving an analog signal from the game controller, the analog signal having a signal level corresponding to a state of a corresponding game controller input device; a bus connector for connecting the circuit board to the computer data and control bus; means for converting the analog signal to a corresponding numeric representation responsive to a "write" sent to the game card by the computer; and means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer, computer responsive to a "read" sent to the game card by the computer; the game card connector including a plurality of analog signals from the game controller; and the means for converting the analog signal to a corresponding numeric representation including means for converting each analog signal to a corresponding numeric representation; and means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer includes means for providing the plurality of said numeric representations at a single address; the means for providing the plurality of numeric representations of said analog signals at a single address including: a loadable counter; logic means for loading the counter with an initial count responsive to a "write" sent to the game card by the computer and incrementing the counter responsive to a "read" sent to the game card by the computer; and means for selecting one of the plurality of numeric representations corresponding to the counter count responsive to a "read" sent to the game card by the computer.

Claim 31

A video game card for interfacing a game controller having one or more input devices to a computer including a microprocessor having data and control buses and a card slot for receiving I/O cards, the game card comprising: a circuit board for mounting electrical components and connectors thereupon, the circuit board sized to fit in the card slot of the personal computer; a game card connector for receiving an analog signal from the game controller, the analog signal having a signal level corresponding to a state of a corresponding game controller input device; a bus connector for connecting the circuit board to the computer data and control bus; means for converting the analog signal to a corresponding numeric representation responsive to a "write" sent to the game card by the computer; and means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer, computer responsive to a "read" sent to the game card by the computer; the game card connector including a plurality of analog signals from the game controller; and the means for converting the analog signal to a corresponding numeric representation including means for converting each analog signal to a corresponding numeric representation; and means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer includes means for providing the plurality of said numeric representations at a single address; the means for providing the plurality of numeric representations of said analog signals at a single address including: a loadable counter; logic means for loading the counter with an initial count responsive to a "write" sent to the game card by the computer and incrementing the counter responsive to a "read" sent to the game card by the computer; and means for selecting one of the plurality of numeric representations corresponding to the counter count responsive to a "read" sent to the game card by the computer.

Claim 32

A video game card according to claim 27 wherein the means for selecting one of the plurality of numeric representations includes: a plurality of latches, each latch storing a numeric representation for a corresponding analog signal; and a decoder interposed between the counter and the plurality of latches, wherein the decoder receives the counter count and enables one the plurality of latches specified by the count responsive to a "read" sent to the game card by the computer.

Claim 33

A video game card according to claim 27 wherein the means for converting each analog signal to a corresponding numeric representation includes: an analog multiplexer having a plurality of inputs coupled to the game card connector for receiving the plurality of analog signals from the game controller and an output for providing a selected one of the plurality of analog signals as a multiplexer output signal; and a converter circuit coupled between the analog multiplexer and the analog to digital converter for converting the multiplexer output signal to a voltage signal and providing the voltage signal to the analog to digital converter.

Claim 34

A game controller interface for interfacing the game controller to a computer, the computer being capable of executing "write" operations to the interface and "read" operations from the interface, the interface comprising: a connector connectable to the game controller for receiving an analog signal from the game controller, the analog signal having a signal level corresponding to a state of a corresponding game controller input device; means for converting the analog signal to a corresponding numeric representation; means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer during a first mode; and a circuit for providing to the computer a digital signal corresponding to the analog signal level during a second mode, the circuit including means for asserting the digital signal responsive to a "write" sent to the interface by the computer and means for deasserting the digital signal responsive to a number of "reads" sent to the interface by the computer, the "read" at which the digital signal is deasserted being determined from the analog signal level.

Claim 35

A game controller interface for interfacing the game controller to a computer, the computer being capable of executing "write" operations to the interface and "read" operations from the interface, the interface comprising: a connector connectable to the game controller for receiving an analog signal from the game controller, the analog signal having a signal level corresponding to a state of a corresponding game controller input device; means for converting the analog signal to a corresponding numeric representation; means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer during a first mode; and a circuit for providing to the computer a digital signal corresponding to the analog signal level during a second mode, the circuit including means for asserting the digital signal responsive to a "write" sent to the interface by the computer and means for deasserting the digital signal responsive to a number of "reads" sent to the interface by the computer, the "read" at which the digital signal is deasserted being determined from the analog signal level.

Claim 36

A game controller interface according to claim 30 further comprising means for switching between the first mode and the second mode.

Claim 37

A game controller interface according to claim 30 wherein the means for switching between the first mode and the second mode includes an address decoder for decoding a first address during the "write" corresponding to the first mode and a second address during the "write" corresponding to the second mode.

Claim 38

A game controller interface according to claim 32 wherein the means for switching between the first mode and the second mode includes: means for selecting the first address; and means for selecting the second address.

Claim 39

A game controller interface according to claim 33 wherein the means for selecting the first address and the means for selecting the second address include a jumper block.

Claim 40

A game controller interface according to claim 30 wherein the means for deasserting the digital signal responsive to a number of "reads" includes means for recording the number of "reads" since the last "write."

Claim 41

A game controller interface according to claim 35 wherein the recording means includes a voltage ramp generator, the voltage ramp generator generates a ramp voltage that is proportional to the number of "reads" since the last "write."

Claim 42

A game controller interface according to claim 36 wherein the voltage ramp generator includes: a digital-to-analog converter; and a counter coupled to the digital-to-analog converter for providing a count thereto, the counter count being incremented responsive to a "read" and being cleared responsive to a "write."

Claim 43

A game controller interface according to claim 35 wherein the recording means includes a counter for storing a read count, the read count being incremented responsive to a "read" and being cleared responsive to a "write."

Claim 44

A game controller interface according to claim 38 further comprising a comparator having a first input coupled to the counter for receiving the read count, a second input coupled to the converting means, and an output for providing a result signal corresponding to the results of the comparison.

Claim 45

A game controller interface according to claim 39 wherein the comparator is a greater-than or equal-to comparator.

Claim 46

A game controller interface according to claim 39 wherein the comparator is an equal-to comparator and wherein the circuit further includes a memory element coupled to the comparator, the memory element being asserted responsive to a "write" and being deasserted responsive to a positive result from the comparator.