US5590116A
Expired / Lapsed
US
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Multiport analyzing, time stamp synchronizing and parallel communicating
Assignee: Wandel & Goltermann Inc
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Filing: 1995-02-09
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Granted: 1996-12-31
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Expires: 2015-02-09
Abstract
Abstract A plurality of digital transmission network analyzers are arranged to analyze and compare the appearance of a data packet on the plurality of ports of a network. Each analyzer has its own internal clock for time stamping of data packets in addition to other internal timing purposes. In order to synchronize the time stamping of the packet as it appears to each analyzer at a each different port, the clock outputs of the several analyzers are connected together; and a controlling CPU commands one of the analyzers to supply the master clock to the others. That master analyzer then commands the other analyzers to disable or disconnect their own clocks, thereby all of the analyzers involved in a given test are under timing control of the clock of the master analyzer. Packet headers and time stamps are transmitted between analyzers for comparison, analysis, and reporting to the controlling CPU. This analyzer intercommunication is done over a separate bus that interconnects all of the analyzers and the controlling CPU.
Inventors
- 👤 Jing Zhang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:30
CPC Classifications
H; H04; H04L; H04L43/00; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0638; H04J3/0658; H04J3/0685; H04J3/0697; H04L7/00; H04L7/0008
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
269 words
An analyzer for digital transmission networks with multiple ports, said analyzer having data packet analyzing capability, a facility for participating in an analysis with at least one other analyzer with which said analyzer is synchronized and in intercommunication outside of the digital transmission networks under the analysis, for said analysis at least two ports of a digital transmission network, said analyzer including: a clock having an output and constituting a part of said analyzer; a counter, the output of which is used to time stamp data packets received by said analyzer, the input of the counter being interconnectable with the output of the clock of said other analyzer; the output of said clock being interconnectable with the input of the counter of said analyzer and to the input of the counter of said other analyzer; a clock control circuit for selectively interconnecting the clock of said analyzer to the counter of said analyzer and to the counter of said other analyzer, and for disconnecting the clock of said analyzer from the counter of said analyzer in response to a clock-disable signal received by said analyzer from a source external to said analyzer, thereby allowing the clock output of said other analyzer to substitute for the output of the disconnected clock of said analyzer; at least one receive-transmit circuit, having a receive mode and a transmit mode, for intercommunicating, separately from said digital transmission network, in either direction with said other analyzer; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from a source external to said analyzer.
Claim 2
Dependent Claim
269 words
An analyzer for digital transmission networks with multiple ports, said analyzer having data packet analyzing capability, a facility for participating in an analysis with at least one other analyzer with which said analyzer is synchronized and in intercommunication outside of the digital transmission networks under the analysis, for said analysis at least two ports of a digital transmission network, said analyzer including: a clock having an output and constituting a part of said analyzer; a counter, the output of which is used to time stamp data packets received by said analyzer, the input of the counter being interconnectable with the output of the clock of said other analyzer; the output of said clock being interconnectable with the input of the counter of said analyzer and to the input of the counter of said other analyzer; a clock control circuit for selectively interconnecting the clock of said analyzer to the counter of said analyzer and to the counter of said other analyzer, and for disconnecting the clock of said analyzer from the counter of said analyzer in response to a clock-disable signal received by said analyzer from a source external to said analyzer, thereby allowing the clock output of said other analyzer to substitute for the output of the disconnected clock of said analyzer; at least one receive-transmit circuit, having a receive mode and a transmit mode, for intercommunicating, separately from said digital transmission network, in either direction with said other analyzer; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from a source external to said analyzer.
Claim 3
Dependent Claim
38 words
An analyzer as set forth in claim 1 further comprising an analysis-control computer (40) for sending control signals to operate the clock control circuit (60, 54, 52C) and for sending commands to operate the receive-transmit control circuit (92).
Claim 4
Dependent Claim
36 words
An analyzer according to claim 1 wherein said clock control circuit is also capable of sending to another network analyzer a clock-disable signal whereby the clock output substitutes for the clock output of said other analyzer.
Claim 5
Dependent Claim
17 words
An analyzer according to claim 3 wherein said received clock-disable signal is received from said other analyzer.
Claim 6
Dependent Claim
39 words
An analyzer according to claim 1 wherein said receive-transmit circuit is a half-duplex circuit and said receive-transmit control circuit determines, in response to said command, whether the receive-transmit circuit is in the receive mode or in the transmit mode.
Claim 7
Dependent Claim
120 words
An analyzer for digital transmission networks with multiple ports, said analyzer having data packet analyzing capability for analyzing digital transmission at one port of a digital transmission network, a facility for participating in an analysis, with at least one other, similar, analyzer analyzing the same digital transmission at another port of said digital transmission network, with intercommunication with said other analyzer, said analyzer including: at least one receive-transmit circuit, having a receive mode and a transmit mode, for intercommunicating, with said other analyzer analyzing the same digital transmission at said other port; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from a source external to said analyzer.
Claim 8
Dependent Claim
120 words
An analyzer for digital transmission networks with multiple ports, said analyzer having data packet analyzing capability for analyzing digital transmission at one port of a digital transmission network, a facility for participating in an analysis, with at least one other, similar, analyzer analyzing the same digital transmission at another port of said digital transmission network, with intercommunication with said other analyzer, said analyzer including: at least one receive-transmit circuit, having a receive mode and a transmit mode, for intercommunicating, with said other analyzer analyzing the same digital transmission at said other port; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from a source external to said analyzer.
Claim 9
Dependent Claim
39 words
An analyzer according to claim 6 wherein said receive-transmit circuit is a half-duplex circuit and said receive-transmit control circuit determines, in response to said command, whether the receive-transmit circuit is in the receive mode or in the transit mode.
Claim 10
Dependent Claim
29 words
An analyzer according to claim 6 wherein said receive-transmit circuit is separate from said digital transmission network and is capable of communicating in either direction with said other analyzer.
Claim 11
Dependent Claim
188 words
An analyzer for digital transmission networks with multiple ports, said analyzer having data packet analyzing capability, a facility for participating, with at least one other analyzer, in an analysis, with intercommunication with said other analyzer, at multiple ports of a digital transmission network, said analyzer including: at least one receive-transmit circuit, separate from said digital transmission network, having a receive mode and a transmit mode, for intercommunicating in either direction, with said other analyzer; a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from source external to said analyzer; a second receive-transmit circuit for intercommunicating, separately from said digital transmission network, in either direction with said other analyzer and alternatively with a third analyzer; and a second receive-transmit control circuit for controlling the transmission and reception capability of the second receive-transmit circuit in response to a command from a source external to said analyzer, whereby simultaneous receiving and transmitting intercommunication is possible between said analyzer and said other analyzer or in a first direction with said other analyzer and in a second direction with said third analyzer.
Claim 12
Dependent Claim
188 words
An analyzer for digital transmission networks with multiple ports, said analyzer having data packet analyzing capability, a facility for participating, with at least one other analyzer, in an analysis, with intercommunication with said other analyzer, at multiple ports of a digital transmission network, said analyzer including: at least one receive-transmit circuit, separate from said digital transmission network, having a receive mode and a transmit mode, for intercommunicating in either direction, with said other analyzer; a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from source external to said analyzer; a second receive-transmit circuit for intercommunicating, separately from said digital transmission network, in either direction with said other analyzer and alternatively with a third analyzer; and a second receive-transmit control circuit for controlling the transmission and reception capability of the second receive-transmit circuit in response to a command from a source external to said analyzer, whereby simultaneous receiving and transmitting intercommunication is possible between said analyzer and said other analyzer or in a first direction with said other analyzer and in a second direction with said third analyzer.
Claim 13
Dependent Claim
269 words
A digital transmission network analyzer system, including a plurality of analyzers, for analyzing a network with multiple ports, the analyzers of said system having data packet analyzing capability, a facility for analyzing a digital transmission network with multiple ports with the analyzer system employing synchronization and intercommunication between the analyzers, comprising: each analyzer of said analyzer system having a local clock having an output, and each analyzer connected to a different port on the network; an analysis-control CPU connected to each of the analyzers for controlling the analyzers of said analyzer system and programming the analyzers of said analyzer system to perform an analysis; the output of the local clock in each of the analyzers being interconnectable with the output of the local clock in each of the other analyzers; a clock control circuit in each analyzer for: sending to the other analyzers a clock-disable signal in response to receipt of a command from the CPU to serve as a master and to provide clock signals for all of the analyzers, whereby the clock output of the analyzer serving as the master is substituted for the clock output of each of the other analyzers, disabling its own local clock in response to receipt of a clock-disable signal from an other analyzer, thereby allowing the clock output of said other analyzer to substitute for the output of its own disabled local clock; at least one receive-transmit circuit for intercommunicating in either direction with the other analyzers; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from the CPU.
Claim 14
Dependent Claim
269 words
A digital transmission network analyzer system, including a plurality of analyzers, for analyzing a network with multiple ports, the analyzers of said system having data packet analyzing capability, a facility for analyzing a digital transmission network with multiple ports with the analyzer system employing synchronization and intercommunication between the analyzers, comprising: each analyzer of said analyzer system having a local clock having an output, and each analyzer connected to a different port on the network; an analysis-control CPU connected to each of the analyzers for controlling the analyzers of said analyzer system and programming the analyzers of said analyzer system to perform an analysis; the output of the local clock in each of the analyzers being interconnectable with the output of the local clock in each of the other analyzers; a clock control circuit in each analyzer for: sending to the other analyzers a clock-disable signal in response to receipt of a command from the CPU to serve as a master and to provide clock signals for all of the analyzers, whereby the clock output of the analyzer serving as the master is substituted for the clock output of each of the other analyzers, disabling its own local clock in response to receipt of a clock-disable signal from an other analyzer, thereby allowing the clock output of said other analyzer to substitute for the output of its own disabled local clock; at least one receive-transmit circuit for intercommunicating in either direction with the other analyzers; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from the CPU.
Claim 15
Dependent Claim
20 words
A digital transmission network analyzer system according to claim 10 wherein the clock-disable signal is received from said other analyzer.
References Cited (Backward Citations)
US4276656A
Cited
US4792753A
Cited
US4916694A
Cited
US5097469A
Cited
US4998240A
Cited
US5247517A
Cited
US5347524A
Cited
US5197127A
Cited
US5276529A
Cited
US5260970A
Cited
US5363493A
Cited
US5282194A
Cited
US5375159A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |