US5585855A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital video signal coding circuit, digital signal decoding circuit
Assignee: Victor Company of Japan Ltd
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Filing: 1994-06-23
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Granted: 1996-12-17
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Expires: 2014-06-23
Abstract
Abstract A digital video signal coding circuit has a first DCT circuit for DCT converting a digital video signal with respect to frame and second DCT circuit for DCT converting the digital video signal with respect to fields which is used to reduce high frequency component of image. These outputs are selected according to high frequency components. The selected signal is separated to two signals respectively coded with data compression through VLC circuits which are provided to speed up the processing speed with non-industrial use ICs. A helical scan video tape recorder records the digital video signal such that at a lower portion (width direction) of slant track on a video tape, video data of an upper screen portion of the first field is recorded, at an upper portion of the track, video data of the upper screen portion of the second field is recorded, at a lower portion of the next slant track, video data of a lower screen portion of the first field is recorded, and at an upper portion, video data of the lower screen portion of the second field is recorded. This provides favorable image on a searching mode.
Inventors
- 👤 Hidetoshi Ozaki
- 👤 Minoru Otani
- 👤 Masaki Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:24
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/20; H04N21/23; H04N21/236; H04N19/00; H04N19/10; H04N19/102; H04N19/103; H04N19/112; H04N21/40; H04N21/43; H04N21/434; H04N5/00; H04N5/76; H04N5/91; H04N5/92; H04N5/926; H04N5/9261; H04N5/9264; H04N5/93; H04N5/78; H04N5/782; H04N5/783
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
427 words
A digital video signal coding circuit for coding digital video data comprising: (a) first orthogonal transforming means for effecting orthogonal transformation to said digital video data at every first unit area of a frame of said digital video data to produce a first set of coefficient data, said frame including first and second fields; (b) first scanning means for scanning said first set of coefficient data in a first predetermined order to produce a first data train including a first set of odd numbered data indicative of said digital video data at every first unit area and a first set of even numbered data indicative of said digital video data at every first unit area; (c) second orthogonal transforming means for effecting orthogonal transformation to said digital video data at every second unit area of said first field and at every third unit area of said second field to produce second and third sets of coefficient data respectively, said first unit area corresponding to said second and third unit areas; (d) second scanning means for scanning said second and third coefficient data in a second predetermined order to produce a second data train including a second set of odd numbered data indicative of said digital video data at every second unit area and a second set of even numbered data indicative of said digital video data at every third unit area; (e) detection means for detecting which one of said first and second frame data trains has a smaller amount of high frequency components to produce a control signal; (f) selecting means .responsive to said control signal, for outputting as a third data train either of said first or second data train; (g) separating means for separating said third data train and outputting said first set of even numbered data as a fourth data train and said first set of odd numbered data as a fifth data train when said selecting means outputs said first data train, and outputting said second set of even numbered data as said fourth data train and said second set of odd numbered data as said fifth data train when said selecting means outputs said second data train; (h) first coding means for effecting a data compression coding to said fourth data train; (i) signal adding means for adding said control signal to said fourth data train from said first coding means to output a first coded video data; and (j) second coding means for effecting said data compression coding to said fifth data train to output a second coded video data.
Claim 2
Dependent Claim
427 words
A digital video signal coding circuit for coding digital video data comprising: (a) first orthogonal transforming means for effecting orthogonal transformation to said digital video data at every first unit area of a frame of said digital video data to produce a first set of coefficient data, said frame including first and second fields; (b) first scanning means for scanning said first set of coefficient data in a first predetermined order to produce a first data train including a first set of odd numbered data indicative of said digital video data at every first unit area and a first set of even numbered data indicative of said digital video data at every first unit area; (c) second orthogonal transforming means for effecting orthogonal transformation to said digital video data at every second unit area of said first field and at every third unit area of said second field to produce second and third sets of coefficient data respectively, said first unit area corresponding to said second and third unit areas; (d) second scanning means for scanning said second and third coefficient data in a second predetermined order to produce a second data train including a second set of odd numbered data indicative of said digital video data at every second unit area and a second set of even numbered data indicative of said digital video data at every third unit area; (e) detection means for detecting which one of said first and second frame data trains has a smaller amount of high frequency components to produce a control signal; (f) selecting means .responsive to said control signal, for outputting as a third data train either of said first or second data train; (g) separating means for separating said third data train and outputting said first set of even numbered data as a fourth data train and said first set of odd numbered data as a fifth data train when said selecting means outputs said first data train, and outputting said second set of even numbered data as said fourth data train and said second set of odd numbered data as said fifth data train when said selecting means outputs said second data train; (h) first coding means for effecting a data compression coding to said fourth data train; (i) signal adding means for adding said control signal to said fourth data train from said first coding means to output a first coded video data; and (j) second coding means for effecting said data compression coding to said fifth data train to output a second coded video data.
Claim 3
Dependent Claim
696 words
A digital video signal coding and decoding circuit for decoding first and second input signals, which are produced by the digital video signal coding circuit for coding digital video data, the digital video signal coding circuit comprising: first orthogonal transforming means for effecting orthogonal transformation to said digital video data at every first unit area of a frame of said digital video data to produce a first set of coefficient data, said frame including first and second fields; first scanning means for scanning said first set of coefficient data in a first predetermined order to produce a first data train including a first set of odd numbered data indicative of said digital video data at every first unit area and a first set of even numbered data indicative of said digital video data at every first unit area; second orthogonal transforming means for effecting orthogonal transformation to said digital video data at every second unit area of said first field and at every third unit area of said second field to produce second and third sets of coefficient data respectively, said first unit area corresponding to said second and third unit areas; second scanning means for scanning said second and third coefficient data in a second predetermined order to produce a second data train including a second set of odd numbered data indicative of said digital video data at every second unit area and a second set of even numbered data indicative of said digital video data at every third unit area; detection means for detecting which one of said first and second frame data trains has a smaller amount of high frequency components to produce a control signal; selecting means for responsive to said control signal, outputting as a third data train either of said first or second data train; separating means for separating said third data train and outputting said first set of even numbered data as a fourth data train and said first set of odd numbered data as a fifth data train when said selecting means outputs said first data train, and outputting said second set of even numbered data as said fourth data train and said second set of odd numbered data as said fifth data train when said selecting means outputs said second data train; first coding means for effecting a data compression coding to said fourth data train; signal adding means for adding said control signal to said fourth data train from said first coding means to output a first coded video data; and second coding means for effecting said data compression coding to said fifth data train to output a second coded video data as said second input signal, the digital video signal decoding circuit comprising: (a) first decoding means for effecting a decoding to said first input signal to reproduce said fourth data train; (b) second decoding means for effecting said decoding to said second input signal to reproduce said fifth data train; (c) mixing means for mixing said reproduced fourth and fifth data trains to reproduce said third data train; (d) first inverse orthogonal transforming means, having a fourth unit area corresponding to said first unit area, for effecting inverse orthogonal transformation; (e) first inverse scanning means for arranging said reproduced third data train from said mixing means on said fourth unit area to reproduce said first set of coefficient data, said first inverse orthogonal transforming means reproducing said digital video data; (f) second inverse orthogonal transforming means having third and fourth field unit areas for effecting inverse orthogonal transformation; (g) second inverse scanning means for arranging said reproduced third data train on said third and fourth field unit areas to reproduce said second and third sets of coefficient data on said third and fourth area respectively, said second inverse orthogonal transforming means reproducing said digital video data from said second and third set of coefficient data; (h) control signal detection means for detecting said control signal from said first coded video data; and (i) switching means responsive to said reproduced control signal for controlling of outputting of said reproduced video data from said first inverse orthogonal transforming means or said second inverse orthogonal transforming means.
Claim 4
Dependent Claim
696 words
A digital video signal coding and decoding circuit for decoding first and second input signals, which are produced by the digital video signal coding circuit for coding digital video data, the digital video signal coding circuit comprising: first orthogonal transforming means for effecting orthogonal transformation to said digital video data at every first unit area of a frame of said digital video data to produce a first set of coefficient data, said frame including first and second fields; first scanning means for scanning said first set of coefficient data in a first predetermined order to produce a first data train including a first set of odd numbered data indicative of said digital video data at every first unit area and a first set of even numbered data indicative of said digital video data at every first unit area; second orthogonal transforming means for effecting orthogonal transformation to said digital video data at every second unit area of said first field and at every third unit area of said second field to produce second and third sets of coefficient data respectively, said first unit area corresponding to said second and third unit areas; second scanning means for scanning said second and third coefficient data in a second predetermined order to produce a second data train including a second set of odd numbered data indicative of said digital video data at every second unit area and a second set of even numbered data indicative of said digital video data at every third unit area; detection means for detecting which one of said first and second frame data trains has a smaller amount of high frequency components to produce a control signal; selecting means for responsive to said control signal, outputting as a third data train either of said first or second data train; separating means for separating said third data train and outputting said first set of even numbered data as a fourth data train and said first set of odd numbered data as a fifth data train when said selecting means outputs said first data train, and outputting said second set of even numbered data as said fourth data train and said second set of odd numbered data as said fifth data train when said selecting means outputs said second data train; first coding means for effecting a data compression coding to said fourth data train; signal adding means for adding said control signal to said fourth data train from said first coding means to output a first coded video data; and second coding means for effecting said data compression coding to said fifth data train to output a second coded video data as said second input signal, the digital video signal decoding circuit comprising: (a) first decoding means for effecting a decoding to said first input signal to reproduce said fourth data train; (b) second decoding means for effecting said decoding to said second input signal to reproduce said fifth data train; (c) mixing means for mixing said reproduced fourth and fifth data trains to reproduce said third data train; (d) first inverse orthogonal transforming means, having a fourth unit area corresponding to said first unit area, for effecting inverse orthogonal transformation; (e) first inverse scanning means for arranging said reproduced third data train from said mixing means on said fourth unit area to reproduce said first set of coefficient data, said first inverse orthogonal transforming means reproducing said digital video data; (f) second inverse orthogonal transforming means having third and fourth field unit areas for effecting inverse orthogonal transformation; (g) second inverse scanning means for arranging said reproduced third data train on said third and fourth field unit areas to reproduce said second and third sets of coefficient data on said third and fourth area respectively, said second inverse orthogonal transforming means reproducing said digital video data from said second and third set of coefficient data; (h) control signal detection means for detecting said control signal from said first coded video data; and (i) switching means responsive to said reproduced control signal for controlling of outputting of said reproduced video data from said first inverse orthogonal transforming means or said second inverse orthogonal transforming means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-17 | 2000-06-17 | 2000-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-17 | 2004-06-17 | 2004-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-17 | 2008-06-17 | 2008-12-17 | $7700.00 | Window Closed / Lapsed |