US5584033A
Expired / Lapsed
US
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Apparatus and method for burst data transfer employing a pause at fixed data intervals
Assignee: International Business Machines Corp
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Filing: 1994-11-07
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Granted: 1996-12-10
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Expires: 2014-11-07
Abstract
Abstract A plurality of devices attached to a communications bus observe a burst transfer protocol which allows pausing only at pre-determined, fixed intervals of n data words, where a word is the width of the bus. In accordance with this protocol, once burst transfer is initialized the sending device transmits an uninterrupted stream of n data words over the communications bus, after which either the sender or receiver may cause transmission to pause. The sender may need to wait for more data, or the receiver may need to finish processing the data just received. The pause lasts as long as needed until both devices are ready to proceed. This cycle is repeated until the data transmission is complete. The sending and receiving devices do not relinquish control of the bus during a pause, and therefore are not required to re-initialize communications. In the preferred embodiment, after n data words have been transmitted, the sender and receiver toggle interlocking signals that accomplish a handshaking between the two devices. The sender de-activates its signal when it is ready to send more, and the receiver de-activates its signal when it is ready to receive more. Both devices are equipped with buffers large enough to hold n data words, but the buffers need not be as large as the longest possible burst communication.
Inventors
- 👤 Wayne M. Barrett
- 👤 Bruce L. Beukema
- 👤 William E. Hammer
- 👤 Daniel F. Moertl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 04:26
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/4226
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
224 words
An apparatus for communicating between devices in a computer system, comprising: an internal system communications bus having a plurality of communications lines; a plurality of bus interface units attached to said communications bus, each of said interface units associated with one of a plurality of processor units, said processor units capable of operating at the same or different speeds from other of said processor units; means for initializing a burst data transmission comprised of a plurality of uninterruptible streams of n data transfer cycles, where n is a predetermined integer greater than one, said burst data transmission between a first of said plurality of bus interface units and a second of said plurality of bus interface units wherein one of said first and second bus interface units takes control of said communications bus and maintains control until said burst data transmission is complete; means in said first bus interface unit for transmitting said burst data to said second bus interface units; means in said second bus interface units for receiving each of said uninterruptible streams of n data transfer cycles; means to guarantee and generate a pause indication after transmission of each of said uninterruptible streams of n data transfer cycles; pause detection means for detecting said pause indication; and pause means responsive to said pause detection means for pausing said burst data transmission.
Claim 2
Independent Claim
224 words
An apparatus for communicating between devices in a computer system, comprising: an internal system communications bus having a plurality of communications lines; a plurality of bus interface units attached to said communications bus, each of said interface units associated with one of a plurality of processor units, said processor units capable of operating at the same or different speeds from other of said processor units; means for initializing a burst data transmission comprised of a plurality of uninterruptible streams of n data transfer cycles, where n is a predetermined integer greater than one, said burst data transmission between a first of said plurality of bus interface units and a second of said plurality of bus interface units wherein one of said first and second bus interface units takes control of said communications bus and maintains control until said burst data transmission is complete; means in said first bus interface unit for transmitting said burst data to said second bus interface units; means in said second bus interface units for receiving each of said uninterruptible streams of n data transfer cycles; means to guarantee and generate a pause indication after transmission of each of said uninterruptible streams of n data transfer cycles; pause detection means for detecting said pause indication; and pause means responsive to said pause detection means for pausing said burst data transmission.
Claim 3
Dependent Claim
36 words
The communications apparatus of claim 1, further comprising means for padding said burst data transmission with additional dummy data to make said burst data transmission an integral multiple of uninterruptible streams of n data transfer cycles.
Claim 4
Dependent Claim
26 words
The communications apparatus of claim 1, wherein said pausing means comprises means for pausing until a ready indication is received from said second bus interface unit.
Claim 5
Dependent Claim
36 words
The communication apparatus of claim 3, wherein said pause indication is a predefined signal level on a predefined communications line of said communications bus, and said ready indication is a change in said predefined signal level.
Claim 6
Dependent Claim
37 words
The communications apparatus of claim 1, further comprising means in at least one of said bus interface units for transmitting status of said bus interface unit after each of said uninterruptible streams of n data transfer cycles.
Claim 7
Dependent Claim
58 words
The communications apparatus of claim 1, wherein said means to guarantee and generate said pause indication further comprises: means in one of said bus interface unit for generating a pause indication after transmission of an uninterruptible stream of n data transfer cycles; and pause detection means in other of said bus interface unit for detecting said pause indication.
Claim 8
Dependent Claim
50 words
The communications apparatus of claim 1, further comprising a buffer in each said bus interface unit, wherein the total buffer space in each said bus interface unit is at least one uninterruptible steam of n data transfer cycles, and is less than the total length of said burst data transmission.
Claim 9
Independent Claim
212 words
A method of communicating data, comprising the steps of: initializing a burst data transmission comprising a plurality of uninterruptible streams of n data transfer cycles between a sender device and a receiver device, said sender device and said receiver device each associated with its own processor, one of said processors capable of operating at the same or at different speeds than the other of said processors, and each of said devices attached to an internal systems communication bus wherein one of said sender and receiver devices takes control of said communications bus and maintains control until said burst data transmission is complete; transmitting from said sender device, and uninterruptible stream of n data transfer cycles to said receiver device, where n is a predetermined integer greater than one; checking by said sender device at the point of a pause indications from said receiver devices to determine if said receiver device can accept more data transfer cycles or if said sender device requires more time to transmit more of said data; pausing, initiated by either said receiver or said sender device, is said step of checking at the point of a pause indications indicates that a pause is necessary; and repeating said transmitting, check and pausing steps to complete said burst data transmission.
Claim 10
Independent Claim
212 words
A method of communicating data, comprising the steps of: initializing a burst data transmission comprising a plurality of uninterruptible streams of n data transfer cycles between a sender device and a receiver device, said sender device and said receiver device each associated with its own processor, one of said processors capable of operating at the same or at different speeds than the other of said processors, and each of said devices attached to an internal systems communication bus wherein one of said sender and receiver devices takes control of said communications bus and maintains control until said burst data transmission is complete; transmitting from said sender device, and uninterruptible stream of n data transfer cycles to said receiver device, where n is a predetermined integer greater than one; checking by said sender device at the point of a pause indications from said receiver devices to determine if said receiver device can accept more data transfer cycles or if said sender device requires more time to transmit more of said data; pausing, initiated by either said receiver or said sender device, is said step of checking at the point of a pause indications indicates that a pause is necessary; and repeating said transmitting, check and pausing steps to complete said burst data transmission.
Claim 11
Dependent Claim
38 words
The method of communicating of claim 8, further comprising the step of padding said burst data transmission with additional dummy data to make the total length of said data transmission an integral multiple of n data transfer cycles.
Claim 12
Dependent Claim
24 words
The method of communicating of claim 8, wherein said pausing step comprises pausing a variable length of time until a ready indication is received.
Claim 13
Dependent Claim
36 words
The method of communicating of claim 10, wherein said wait indication is a predefined signal level on a signal line of said communications bus, and wherein said ready indication is a change in said signal level.
Claim 14
Dependent Claim
123 words
The method of communicating of claim 8, wherein said sender device and said receiver device each contain a buffer for storage of data being transmitted, the total buffer space in each said device being at least n data transfer cycles, and less than the total length of said burst data transmission, said method further comprising the steps of: placing a first stream of n data transfer cycles in the buffer of said sender device before transmitting said first stream of n data transfer cycles to said receiver device; and placing a second stream of n data transfer cycles in the buffer of said sender device after transmitting at least part of said first stream of n data transfer cycles to said receiver device.
Claim 15
Independent Claim
171 words
A method of communicating data, comprising the steps of: initializing a burst data transmission comprised of a plurality of uninterruptible streams of n data transfer cycles, where n is a predetermined integer greater than one between a sender device and a receiver device, each of said sender device and said receiver device associated with its own processor capable of operating at the same or at different speed than the other of said processor associated with the other of said devices and each of said devices attached to an internal systems communication bus, wherein one of said sender and receiver devices takes control of said communications bus and maintains control until said burst data transmission is complete; transmitting, with said sender device, an uninterrupted stream of n data transfer cycles, where n is a predetermined integer greater than one; acknowledging, with said receiver device, receipt of said stream of n data transfer cycles; repeating said transmitting and acknowledging steps to complete said burst data transmission; and relinquishing control of said communications bus.
Claim 16
Independent Claim
171 words
A method of communicating data, comprising the steps of: initializing a burst data transmission comprised of a plurality of uninterruptible streams of n data transfer cycles, where n is a predetermined integer greater than one between a sender device and a receiver device, each of said sender device and said receiver device associated with its own processor capable of operating at the same or at different speed than the other of said processor associated with the other of said devices and each of said devices attached to an internal systems communication bus, wherein one of said sender and receiver devices takes control of said communications bus and maintains control until said burst data transmission is complete; transmitting, with said sender device, an uninterrupted stream of n data transfer cycles, where n is a predetermined integer greater than one; acknowledging, with said receiver device, receipt of said stream of n data transfer cycles; repeating said transmitting and acknowledging steps to complete said burst data transmission; and relinquishing control of said communications bus.
Claim 17
Dependent Claim
37 words
The method of communicating of claim 13, further comprising the step of padding said burst data transmission with additional data to make the total length of said data transmission an intergral multiple of n data transfer cycles.
Claim 18
Dependent Claim
90 words
The method of communicating of claim 13, wherein said acknowledging step comprises the steps of: driving, with said receiver device, a first signal line of said communications bus with a predefined signal level during a predefined time interval following transmission of (n-1) transfer cycles of said uninterruptible stream of n data transfer cycles; and driving, with said sender device, a second signal line of said communications bus with a predefined signal level during a predefined time interval following said step of driving, with said receiver device, said first signal line.
Claim 19
Dependent Claim
39 words
The method of communicating of claim 15, wherein said acknowledging step further comprises the step of: driving, with said receiver device, a portion of said communications bus with a plurality of signals indicating the status of said receiver device.
Claim 20
Dependent Claim
41 words
The method of communicating of claim 15, wherein said step of driving, with said receiver device, said first signal line comprises holding said first signal line at said predefined signal level until said receiver device is ready to receive more data.
Claim 21
Dependent Claim
41 words
The method of communicating of claim 17, wherein said step of driving, with said sender device, said second signal line comprises holding said second signal line at said predefined signal level until said sender device is ready to transmit more data.
Claim 22
Dependent Claim
216 words
A first bus interface unit attaching to a communications bus of a computer system, said first bus interface unit comprising: means for initializing a burst data transmission comprised of a plurality of uninterruptible streams of n data transfer cycles, where n is a predetermined integer greater than one, said burst data transmission between said first and a second bus interface unit, each of said first and second bus interface unit associated with its own processor, said processors capable of operating at the same or different speeds, and both of said first and second bus interface units attached to an internal system communications bus, wherein said first bus interface unit takes control of said communications bus and maintains control until said burst data transmission is complete; means for successively transmitting uninterrupted streams of n data transfer cycles in said burst data transmission to said second unit, where n is predetermined integer greater than one; pause detection means for detecting a pause indication from said second bus interface unit at intervals between said uninterrupted streams of n data transfer cycles, said second bus interface unit generating said pause indication when said second bus interface unit is unable to accept more data; and means responsive to said pause detection means for pausing said burst data transmission at said intervals.
Claim 23
Dependent Claim
216 words
A first bus interface unit attaching to a communications bus of a computer system, said first bus interface unit comprising: means for initializing a burst data transmission comprised of a plurality of uninterruptible streams of n data transfer cycles, where n is a predetermined integer greater than one, said burst data transmission between said first and a second bus interface unit, each of said first and second bus interface unit associated with its own processor, said processors capable of operating at the same or different speeds, and both of said first and second bus interface units attached to an internal system communications bus, wherein said first bus interface unit takes control of said communications bus and maintains control until said burst data transmission is complete; means for successively transmitting uninterrupted streams of n data transfer cycles in said burst data transmission to said second unit, where n is predetermined integer greater than one; pause detection means for detecting a pause indication from said second bus interface unit at intervals between said uninterrupted streams of n data transfer cycles, said second bus interface unit generating said pause indication when said second bus interface unit is unable to accept more data; and means responsive to said pause detection means for pausing said burst data transmission at said intervals.
Claim 24
Dependent Claim
48 words
The first bus interface unit of claim 19, further comprising a buffer for storage of data being transmitted, wherein the total buffer space in said first bus interface unit is a least n data transfer cycles, and is less than the total length of said burst data transmission.
Claim 25
Dependent Claim
38 words
The first bus interface unit of claim 19, further comprising means for padding said burst data transmission with additional dummy data to make the total length of said data transmission an integral multiple of n data transfer cycles.
Claim 26
Dependent Claim
27 words
The first bus interface unit of claim 19, wherein said pausing means comprises means for pausing until a ready indication is received from said second bus unit.
Claim 27
Dependent Claim
38 words
The first bus interface unit of claim 22, wherein said pause indication is a predefined signal level on a predefined communications line of said communications bus, and said ready indication is a change in said predefined signal level.
Claim 28
Dependent Claim
155 words
The first bus interface unit of claim 19, wherein said first bus unit is capable of operating in receive mode, wherein said second bus unit is capable of operating in send mode, and wherein said second unit comprises means for successively transmitting a plurality of uninterruptible streams of n data transfer cycles in a burst data transmission to said first unit, pause detection means for detecting a pause indication from said first bus interface unit at intervals between each of said uninterruptible streams of n data transfer cycles, and means responsive to said pause detection means for pausing said burst data transmission at said intervals, said first bus interface unit further comprising: means for receiving each of said uninterruptible streams of n data transfer cycles when operating in receive mode; and means for generating a pause indication after receipt of each of said uninterruptible streams of n data transfer cycles when operating in receive mode.
Claim 29
Dependent Claim
33 words
The first bus interface unit of claim 24, wherein said means for generating a pause indication comprises means for driving a predefined signal level on a predefined communications line of said communications bus.
Claim 30
Dependent Claim
38 words
The first bus interface unit of claim 25, further comprising means for padding said burst data transmission with additional dummy data to make the total length of said data transmission an integral multiple of n data transfer cycles.
Claim 31
Dependent Claim
163 words
A first bus interface unit comprising: means for initializing a burst data transmission between said first and a second bus interface unit, both of said interface units attached to an internal system communications bus and each of said interface units associated with its own processor capable of operating at the same or different speeds than said processor associated with the other of said interface unit, wherein said first bus interface unit takes control of said communications bus and maintains control until said burst data transmission is complete; means for receiving successive uninterrupted streams of n data transfer cycles from said second bus interface unit, where n is a predetermined integer greater than one, said uninterrupted streams of n data transfer cycles being part of a single burst data transmission; and means for generating a pause indication after receipt of an uninterrupted stream of n data transfer cycles, said generating means operating when said first bus interface unit is unable to accept more data.
Claim 32
Dependent Claim
163 words
A first bus interface unit comprising: means for initializing a burst data transmission between said first and a second bus interface unit, both of said interface units attached to an internal system communications bus and each of said interface units associated with its own processor capable of operating at the same or different speeds than said processor associated with the other of said interface unit, wherein said first bus interface unit takes control of said communications bus and maintains control until said burst data transmission is complete; means for receiving successive uninterrupted streams of n data transfer cycles from said second bus interface unit, where n is a predetermined integer greater than one, said uninterrupted streams of n data transfer cycles being part of a single burst data transmission; and means for generating a pause indication after receipt of an uninterrupted stream of n data transfer cycles, said generating means operating when said first bus interface unit is unable to accept more data.
Claim 33
Dependent Claim
48 words
The first bus interface unit of claim 27, further comprising a buffer for storage of data being transmitted, wherein the total buffer space in said first bus interface unit is at least n data transfer cycles, and is less than the total length of said burst data transmission.
Claim 34
Dependent Claim
26 words
The first bus interface unit of claim 27, further comprising means for generating a ready indication when said first unit is ready to receive additional data.
Claim 35
Dependent Claim
38 words
The first bus interface unit of claim 29, wherein said pause indication is a predefined signal level on a predefined communications line of said communications bus, and said ready indication is a change in said predefined signal level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |