Connector arrangement for a semiconductor memory device

Claim 1

A connector arrangement for a semiconductor memory device having a memory cell array comprising a plurality of memory cells on a semiconductor substrate and a peripheral circuit region formed on the periphery of said memory cell array, a memory cell adjacent said peripheral circuit region having a transistor comprised of a source region and a drain region disposed in said substrate, and a gate electrode and a capacitor disposed substantially above said transistor comprised of a storage electrode, a dielectric film and a plate electrode, said connector arrangement comprising: a first conductive layer formed above said transistor and connecting with said gate electrode through a first contact hole at a cell array edge; a first insulating film formed on said first conductive layer; a second contact hole formed on a portion of the source region of said transistor; a storage electrode connector connecting with said source region of said transistor via said second contact hole to said storage electrode formed above said first insulating film; and a second conductive layer disposed in said peripheral circuit region and connected to first conductive layer at a portion where said memory cell array is adjacent said peripheral circuit region.