← Back to Patent Explorer
US5581228A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital signal comparison circuit in a performance monitoring and test system

Assignee: Viavi Solutions Inc
•
Filing: 1995-05-26
•
Granted: 1996-12-03
•
Expires: 2015-05-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A DS3 level access, monitor and test system including a digital comparator for a telephone network. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Inventors

  • 👤 Kevin Cadieux
  • 👤 Paul R. Hartmann
  • 👤 Kevin Pope

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 18:13
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0623; H04J3/0602; H04J3/0605; H04J3/0608; H04J3/14; H04M; H04M3/00; H04M3/22; H04M3/24; H04M3/244

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 72 words
In a telephone network, a compare circuit for two digital signals, comprising: a delay for one of the signals; an m-bit shift register for receiving the signal from the delay; an n-bit shift register for receiving the other signal; and an m-bit comparator for simultaneously comparing each of the m-bits with one of the n bits, wherein at least one of the signals is indicative of a signal in the telephone network.
Claim 2
Dependent Claim 72 words
In a telephone network, a compare circuit for two digital signals, comprising: a delay for one of the signals; an m-bit shift register for receiving the signal from the delay; an n-bit shift register for receiving the other signal; and an m-bit comparator for simultaneously comparing each of the m-bits with one of the n bits, wherein at least one of the signals is indicative of a signal in the telephone network.
Claim 3
Dependent Claim 28 words
The compare circuit defined in claim 1, wherein a comparison is made having up to the absolute value of m-n bits of latency between the two digital signals.
Claim 4
Dependent Claim 29 words
The compare circuit defined in claim 1, wherein the m-bit shift register is a seven bit shift register and the n-bit shift register is a four bit shift register.
Claim 5
Dependent Claim 15 words
The compare circuit defined in claim 1, wherein each digital signal comprises a DS3 signal.
Claim 6
Dependent Claim 32 words
The compare circuit defined in claim 1, additionally comprising a switch control circuit, receivably connected to the ouput of the m-bit comparator, to control which digital signal is processed by other circuits.
Claim 7
Dependent Claim 61 words
In a telephone network, a method for comparing two digital signals, comprising the steps of: delaying one of the signals, received from the telephone network; storing m bits of the delayed signal; storing n bits of the other signal; simultaneously comparing each of the m bits with one of the n bits; and generating a compare signal based upon the comparison.
Claim 8
Dependent Claim 61 words
In a telephone network, a method for comparing two digital signals, comprising the steps of: delaying one of the signals, received from the telephone network; storing m bits of the delayed signal; storing n bits of the other signal; simultaneously comparing each of the m bits with one of the n bits; and generating a compare signal based upon the comparison.
Claim 9
Dependent Claim 28 words
The method defined in claim 6, wherein the m-bit shift register is a seven bit shift register and the n-bit shift register is a four bit shift register.
Claim 10
Dependent Claim 14 words
The method defined in claim 6, wherein each digital signal comprises a DS3 signal.
Claim 11
Dependent Claim 15 words
The method defined in claim 6, wherein a hitless switch is made between the signals.

References Cited (Backward Citations)

US4771421A Cited
WO1986005054A1 Cited
US4757464A Cited
US4786168A Cited
US4993013A Cited
US5138616A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-12-03 2000-06-03 2000-12-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-12-03 2004-06-03 2004-12-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-12-03 2008-06-03 2008-12-03 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag