US5579234A
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US
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System for automatically testing an electronic device during quiescent periods
Assignee: Physio Control Inc
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Filing: 1994-03-11
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Granted: 1996-11-26
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Expires: 2014-03-11
Abstract
Abstract A portable electronic unit, such as a defibrillator, includes an autotest system for automatically self-testing various electrical components within the unit during quiescent periods. The autotest system includes an autotest routine that performs an extensive array of rigorous yet time-consuming tests that are impractical to perform during normal modes of operation of the unit. A real-time clock can be set to initiate the autotest routine at a time when the unit is unlikely to be used for its normal mode of operation. The autotest system provides a strip chart printout of the results of the various self-tests performed on the unit, and provides messages on a visual display of any error conditions. If the autotest system detects a needs service malfunction, the operator must acknowledge the error with an input to the unit before the unit will enter into its normal mode of operation. If the autotest system detects a service mandatory malfunction, the unit will discontinue any normal mode of operation until the malfunction is corrected. The autotest system immediately discontinues the autotest routine upon power-up of the unit by an operator for use of the unit in its normal mode of operation.
Inventors
- 👤 Robert A. Wiley
- 👤 Abraham H. Kou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:57
CPC Classifications
A; A61; A61N; A61N1/00; A61N1/18; A61N1/32; A61N1/38; A61N1/39; A61N1/3925; A61N1/3931; A61N1/3904; G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/30; G06F11/32; G06F11/321
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
111 words
A method of testing a plurality of circuits in an electronic system having an active mode of operation and a quiescent mode of operation, comprising the steps of: determining if the electronic system is in a quiescent mode of operation; testing an operation of at least a first circuit if the electronic system is in the quiescent mode of operation, the testing of the first circuit being impractical during a non-quiescent mode of operation of the electronic system; storing the results of the tested operation of the first circuit; and providing a first indication to an operator of the electronic system if the tested operation of the first circuit is unacceptable.
Claim 2
Independent Claim
111 words
A method of testing a plurality of circuits in an electronic system having an active mode of operation and a quiescent mode of operation, comprising the steps of: determining if the electronic system is in a quiescent mode of operation; testing an operation of at least a first circuit if the electronic system is in the quiescent mode of operation, the testing of the first circuit being impractical during a non-quiescent mode of operation of the electronic system; storing the results of the tested operation of the first circuit; and providing a first indication to an operator of the electronic system if the tested operation of the first circuit is unacceptable.
Claim 3
Dependent Claim
59 words
The method of claim 1 wherein the step of determining if the electronic system is in a quiescent mode of operation includes the steps of: counting at selected intervals; determining if a count is equal to a predetermined value; and determining whether the electronic system is in a power-down mode if the count is equal to the predetermined value.
Claim 4
Dependent Claim
35 words
The method of claim 2, further comprising the steps of: monitoring whether the electronic system enters into a power-up mode; and halting the step of testing if the electronic system enters into the power-up mode.
Claim 5
Dependent Claim
58 words
The method of claim 1 wherein the step of determining if the electronic system is in a quiescent mode of operation includes the steps of: determining if the electronic system is in a battery charging mode of operation; and suspending the battery charging mode of operation during the duration of the test of at least a first circuit.
Claim 6
Dependent Claim
39 words
The method of claim 1, further comprising the steps of: monitoring whether the electronic system remains in the quiescent mode of operation; and halting the step of testing if the electronic system enters into a non-quiescent mode of operation.
Claim 7
Dependent Claim
17 words
The method of claim 1, further comprising the step of testing the operation of a second circuit.
Claim 8
Dependent Claim
22 words
The method of claim 6 wherein the first circuit is a memory circuit and the second circuit is an analog-to-digital converter circuit.
Claim 9
Dependent Claim
22 words
The method of claim 6 wherein the first circuit is a charging circuit and the second circuit is a transfer relay circuit.
Claim 10
Dependent Claim
50 words
The method of claim 6, further comprising the step of providing a second indication to the operator if the tested operation of the second circuit is unacceptable, wherein the second indication halts normal operation of the electronic system until an input from the operator is received by the electronic system.
Claim 11
Dependent Claim
21 words
The method of claim 9 wherein the first indication is a visual indication and the second indication is an audible indication.
Claim 12
Dependent Claim
25 words
The method of claim 1, further comprising the step of providing a written report indicating a result of the tested operation of the first circuit.
Claim 13
Independent Claim
152 words
An apparatus for testing a plurality of circuits in an electronic system having an active mode of operation and a quiescent mode of operation, comprising: a counter for counting at regular intervals and outputting a counter signal indicating a current value of the counter; a processor circuit coupled to a least a first circuit of the plurality of circuits and the counter for (1) comparing the counter signal to a predetermined value, (2) determining whether the electronic system is in the quiescent mode of operation if the counter signal equals the predetermined value, (3) testing at least the first circuit and (4) outputting a first test result signal indicating a result of the testing; storage means coupled to the processor for storing a result of the testing; and an indication circuit coupled to the processor circuit and outputting a first indication to an operator in response to the first test result signal.
Claim 14
Independent Claim
152 words
An apparatus for testing a plurality of circuits in an electronic system having an active mode of operation and a quiescent mode of operation, comprising: a counter for counting at regular intervals and outputting a counter signal indicating a current value of the counter; a processor circuit coupled to a least a first circuit of the plurality of circuits and the counter for (1) comparing the counter signal to a predetermined value, (2) determining whether the electronic system is in the quiescent mode of operation if the counter signal equals the predetermined value, (3) testing at least the first circuit and (4) outputting a first test result signal indicating a result of the testing; storage means coupled to the processor for storing a result of the testing; and an indication circuit coupled to the processor circuit and outputting a first indication to an operator in response to the first test result signal.
Claim 15
Dependent Claim
20 words
The apparatus of claim 12 wherein the counter is a real-time clock and the predetermined value is a predetermined time.
Claim 16
Dependent Claim
28 words
The apparatus of claim 12 wherein the processor circuit halts testing the operation of the first circuit if the electronic system enters into the active mode of operation.
Claim 17
Dependent Claim
39 words
The apparatus of claim 12 wherein the indicator circuit includes a printer circuit for printing a written report in response to the first test result signal, the written report indicating the result of the testing of the first circuit.
Claim 18
Dependent Claim
38 words
The apparatus of claim 12 wherein the processor circuit outputs the first test result signal if the result of the testing is unacceptable and outputs a second test result signal if the result of the testing is acceptable.
Claim 19
Dependent Claim
67 words
The apparatus of claim 16, further comprising a second circuit coupled to the processor circuit, and wherein the processor circuit outputs a third test result signal if the testing of the second circuit is unacceptable, and wherein the visual indication circuit outputs a first visual indication in response to the first test result signal and a second visual indication in response to the third test result signal.
Claim 20
Dependent Claim
30 words
The apparatus of claim 17, further comprising a switch, and wherein the processor circuit requires the operator to actuate the switch if the testing of the second circuit is unacceptable.
Claim 21
Dependent Claim
55 words
The apparatus of claim 18 wherein the first circuit is a data storage device, the second circuit is a monitoring circuit for use in monitoring a status of a physical condition in a person, and the testing of the second circuit includes applying a known load to the second circuit and measuring a response therefrom.
Claim 22
Dependent Claim
27 words
The apparatus of claim 12, further comprising an audible indicator coupled to the processor circuit for producing an audible indication in response to the first test signal.
Claim 23
Independent Claim
128 words
An apparatus for testing a plurality of circuits in an electronic system having an active mode of operation and a quiescent mode of operation, comprising: a processor circuit coupled to at least a first circuit of the plurality of circuits for (1) determining whether the electronic system is in the quiescent mode of operation, (2) testing at least the first circuit if the electronic system is in the quiescent mode of operation, (3) outputting a first test result signal indicating a result of the testing, and (4) halting testing of the first circuit if the electronic system enters the active mode of operation; and an indication circuit coupled to the processor circuit and outputting a first indication to an operator in response to the first test result signal.
Claim 24
Independent Claim
128 words
An apparatus for testing a plurality of circuits in an electronic system having an active mode of operation and a quiescent mode of operation, comprising: a processor circuit coupled to at least a first circuit of the plurality of circuits for (1) determining whether the electronic system is in the quiescent mode of operation, (2) testing at least the first circuit if the electronic system is in the quiescent mode of operation, (3) outputting a first test result signal indicating a result of the testing, and (4) halting testing of the first circuit if the electronic system enters the active mode of operation; and an indication circuit coupled to the processor circuit and outputting a first indication to an operator in response to the first test result signal.
Claim 25
Dependent Claim
119 words
In a defibrillator circuit having an ECG preamplifier, an impedance circuit and an analog-to-digital converter, a method of testing the defibrillator circuit comprising the steps of: providing a voltage pulse signal to an input of the ECG preamplifier; analyzing a first ECG output signal produced by the ECG preamplifier in response to the voltage pulse signal; determining if the first ECG output signal is acceptable; providing a known impedance signal to an input of the impedance circuit; analyzing a first impedance output signal produced by the impedance circuit in response to the impedance signal; determining if the first impedance output signal is acceptable; and providing a first indication to an operator if any of the determining steps are unacceptable.
Claim 26
Dependent Claim
119 words
In a defibrillator circuit having an ECG preamplifier, an impedance circuit and an analog-to-digital converter, a method of testing the defibrillator circuit comprising the steps of: providing a voltage pulse signal to an input of the ECG preamplifier; analyzing a first ECG output signal produced by the ECG preamplifier in response to the voltage pulse signal; determining if the first ECG output signal is acceptable; providing a known impedance signal to an input of the impedance circuit; analyzing a first impedance output signal produced by the impedance circuit in response to the impedance signal; determining if the first impedance output signal is acceptable; and providing a first indication to an operator if any of the determining steps are unacceptable.
Claim 27
Dependent Claim
97 words
The method of claim 22, further comprising the steps of: providing a first voltage signal to the inputs of the ECG preamplifier and the impedance circuit; analyzing a second ECG output signal produced by the ECG preamplifier and a second impedance output signal produced by the impedance circuit both in response to the first voltage signal; determining if the second ECG output signal and the second impedance output signal are acceptable; and providing a second indication to the operator if at least one of the second ECG output signal and the second impedance output signal are unacceptable.
Claim 28
Dependent Claim
110 words
The method of testing of claim 22, further comprising the steps of: providing a second voltage signal to an input of the analog-to-digital converter; analyzing a first converter output signal produced by the analog-to-digital converter in response to the second voltage signal; determining if the first converter output signal is acceptable; providing a third voltage signal to the input of the analog-to-digital converter; analyzing a second converter output signal produced by the analog-to-digital converter in response to the third voltage signal; determining if the second converter output signal is acceptable; and providing a third indication to the operator if one of the first and second converter output signals are unacceptable.
Claim 29
Dependent Claim
168 words
A self test system for testing a plurality of circuits in a defibrillator having an active mode of operation and a quiescent mode of operation, the self test system comprising: (a) a timer for generating a system time; (b) a processor coupled to the timer and entering a test mode at a predetermined system time, during the test mode the processor determining whether the defibrillator is in a quiescent mode of operation and executing a test of at least one of the plurality of circuits in the defibrillator if the defibrillator is in a quiescent mode of operation, the test producing a result indicative of the status of the tested one of the plurality of circuits; (c) storage means coupled to the processor for storing the test result of at least one of the plurality of circuits; (d) indication means coupled to the processor and the storage means for outputting an indication to an operator of the test result of at least one of the plurality of circuits.
Claim 30
Dependent Claim
168 words
A self test system for testing a plurality of circuits in a defibrillator having an active mode of operation and a quiescent mode of operation, the self test system comprising: (a) a timer for generating a system time; (b) a processor coupled to the timer and entering a test mode at a predetermined system time, during the test mode the processor determining whether the defibrillator is in a quiescent mode of operation and executing a test of at least one of the plurality of circuits in the defibrillator if the defibrillator is in a quiescent mode of operation, the test producing a result indicative of the status of the tested one of the plurality of circuits; (c) storage means coupled to the processor for storing the test result of at least one of the plurality of circuits; (d) indication means coupled to the processor and the storage means for outputting an indication to an operator of the test result of at least one of the plurality of circuits.
Claim 31
Dependent Claim
33 words
The self test system of claim 25, wherein the test of at least one of the plurality of circuits in the defibrillator is halted if the defibrillator enters an active mode of operation.
Claim 32
Dependent Claim
27 words
The self test system of claim 25, wherein the indication means includes a printer circuit for printing a written report of the test result for the operator.
Claim 33
Dependent Claim
26 words
The self test system of claim 25, wherein the indication means includes a display to provide a visual indication of the test result to the operator.
Claim 34
Dependent Claim
27 words
The self test system of claim 25, wherein the indication means includes an audio circuit to provide an auditory indication of the test result to the operator.
References Cited (Backward Citations)
US4164946A
Cited
US4631701A
Cited
US5020541A
Cited
US5097830A
Cited
US5453992A
Cited
US5431684A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-26 | 2008-05-27 | 2008-11-26 | $7700.00 | Window Closed / Lapsed |