Memory access control method wherein block access is performed as a sequential access to an address updated by incrementation

Claim 2

A memory access control method comprising the steps of: receiving address data of an access request; discriminating whether a row address of the received address data accords with a row address of preceding access address data held in a latch; discriminating whether a column address of the received address data is greater than a column address of the preceding access address data held in the latch; successively incrementing a column address of an access address to a memory in a predetermined cycle, from the column address of the preceding address up to the column address of the received address data, and fixing a row address of the access address as the row address of the preceding access address if the row address of the received address data is determined to accord with the row address of the preceding access address data and if the column address of the received address data is determined to be greater than the column address of the preceding access address data, as results obtained in said discriminating steps; successively performing access to the memory with the access address each time the column address of the access address is incremented in said incrementing step; and updating the access address data held in the latch by the access address each time the column address of the access address is incremented in said incrementing step.

Claim 3

A method according to claim 1, further comprising a step of asserting a row address strobe and disasserting a column address strobe after performing the access to the memory.

Claim 4

A method according to claim 1, wherein update of the address data held in the latch is executed each time the access address to the memory is incremented.

Claim 5

An information processing system comprising: memory means for storing information; reception means for receiving address data on a requested access to said memory means; address memory means for storing address data used for a preceding access; discriminating means for discriminating whether a row address of the address data received by said reception means accords with a row address of the preceding access stored in said address memory means and discriminating whether a column address of the address data received by said reception means is greater than a column address of the preceding access stored in said address memory means; increment means for successively incrementing a column address of an access address to said memory means in a predetermined cycle, from the column address of the preceding address up to the column address of the address data received by said reception means, and fixing a row address of the access address as the row address of the preceding access address if the row address of the received address data is determined to accord with the row address of the preceding access and if the column address of the received address data is determined to be greater than the column address of the preceding access, as results obtained by said discriminating means; access means for successively performing access to said memory means with the access address each time the column address of the access address is incremented by said increment means; and update means for updating address data stored in said address memory means by the access address each time the column address of the access address is incremented by said increment means.

Claim 6

An information processing system comprising: memory means for storing information; reception means for receiving address data on a requested access to said memory means; address memory means for storing address data used for a preceding access; discriminating means for discriminating whether a row address of the address data received by said reception means accords with a row address of the preceding access stored in said address memory means and discriminating whether a column address of the address data received by said reception means is greater than a column address of the preceding access stored in said address memory means; increment means for successively incrementing a column address of an access address to said memory means in a predetermined cycle, from the column address of the preceding address up to the column address of the address data received by said reception means, and fixing a row address of the access address as the row address of the preceding access address if the row address of the received address data is determined to accord with the row address of the preceding access and if the column address of the received address data is determined to be greater than the column address of the preceding access, as results obtained by said discriminating means; access means for successively performing access to said memory means with the access address each time the column address of the access address is incremented by said increment means; and update means for updating address data stored in said address memory means by the access address each time the column address of the access address is incremented by said increment means.

Claim 7

A system according to claim 4, further comprising control means for asserting a row address strobe and disasserting a column address strobe after said access means performs the access to said memory means.

Claim 8

A system according to claim 4, wherein the updating of the address stored in said address memory means by said update means is executed each time said increment means increments the access address to said memory means.