Timing phase detector and timing recovery using the same

Claim 2

A timing phase detector using quadrature amplitude modulation comprising: a 4-point fast Fourier transforming portion for Fourier-transforming a digital output signal from an analog-to-digital converter to provide. an output signal; a sum-dump portion for adding and outputting the output signal of said 4-point fast Fourier transforming portion; and a cordic portion for calculating the phase of a complex number so as to indicate the output of said sum/dump portion on an X-Y coordinate.

Claim 3

A timing phase detector using quadrature amplitude modulation as claimed in claim 1, wherein said sum/dump portion comprises: a pair of adders for receiving the output signal of said 4-point fast Fourier transforming portion as one input and providing an output; and a pair of registers for storing the output of said adders, sending back the stored output to said adders as a second input, and repeatedly storing the added value to output the value at the same time.

Claim 4

A timing recovery arrangement using quadrature amplitude modulation comprising: a 4-point fast Fourier transforming portion for Fourier-transforming a digital output signal from an analog-to-digital converter to provide an output signal; a sum/dump portion for adding and outputting the output signal of said 4-point fast Fourier transforming portion; a phase shifter for phase-shifting the output of said sum/dump portion by 90° , and providing a phase-shifted output; and a cordic portion for receiving the phase-shifted output and calculating the phase of a complex number so as to indicate the phase-shifted output on an X-Y coordinate.

Claim 5

A timing recovery arrangement using quadrature amplitude modulation comprising: a 4-point fast Fourier transforming portion for Fourier-transforming a digital output signal from an analog-to-digital converter to provide an output signal; a sum/dump portion for adding and outputting the output signal of said 4-point fast Fourier transforming portion; a phase shifter for phase-shifting the output of said sum/dump portion by 90° , and providing a phase-shifted output; and a cordic portion for receiving the phase-shifted output and calculating the phase of a complex number so as to indicate the phase-shifted output on an X-Y coordinate.

Claim 6

A timing recovery arrangement using a quadrature amplitude modulation as claimed in claim 3, wherein said phase shifter comprises a sign converter for performing sign conversion according to a sign conversion selection signal.

Claim 7

A timing recovery arrangement using quadrature amplitude modulation comprising: an A/D converter for receiving a baseband analog input signal and producing an output digital signal; a 4-point FFT portion for receiving said output digital signal of said A/D converter and obtaining an FFT value by using a shift register, an adder, and a subtractor to produce output signals; a sum/dump portion of a pair of sum/dump for adding the output signals of said 4-point FFT portion sixteen times, respectively, so as to perform a 64-point individual FFT function; a phase shift portion of a pair of phase shifters for receiving outputs of said sum/dumps, and shifting their phases by 90° or -90° according to a selection signal so that if the error is large, the gain of a timing phase detector becomes large to quicken the convergence speed, and if the error is small, the gain becomes small to obtain a stable clock after the convergence; Pl a cordic portion of a pair of cordics for calculating the phase of a complex number input so as to indicate 90°-phase-shifted or -90°-phase-shifted outputs of said phase shifters on an X-Y coordinate; a subtracting portion for obtaining the difference between one output signal of said cordic portion, which has the phase of signal component +1/2 of a symbol frequency, and the other output signal of said cordic portion, which has the phase of signal component -1/2 of the symbol frequency, and providing a timing phase error estimation value as an output; a loop filter for receiving the output of said subtracting portion and providing it as a timing phase error estimation value output; and a voltage-controlled oscillator for receiving said timing phase error estimation value output from said loop filter. and for applying a clock-generating signal to said A/D converter in accordance therewith.

Claim 8

A timing recovery arrangement using quadrature amplitude modulation comprising: an A/D converter for receiving a baseband analog input signal and producing an output digital signal; a 4-point FFT portion for receiving said output digital signal of said A/D converter and obtaining an FFT value by using a shift register, an adder, and a subtractor to produce output signals; a sum/dump portion of a pair of sum/dump for adding the output signals of said 4-point FFT portion sixteen times, respectively, so as to perform a 64-point individual FFT function; a phase shift portion of a pair of phase shifters for receiving outputs of said sum/dumps, and shifting their phases by 90° or -90° according to a selection signal so that if the error is large, the gain of a timing phase detector becomes large to quicken the convergence speed, and if the error is small, the gain becomes small to obtain a stable clock after the convergence; Pl a cordic portion of a pair of cordics for calculating the phase of a complex number input so as to indicate 90°-phase-shifted or -90°-phase-shifted outputs of said phase shifters on an X-Y coordinate; a subtracting portion for obtaining the difference between one output signal of said cordic portion, which has the phase of signal component +1/2 of a symbol frequency, and the other output signal of said cordic portion, which has the phase of signal component -1/2 of the symbol frequency, and providing a timing phase error estimation value as an output; a loop filter for receiving the output of said subtracting portion and providing it as a timing phase error estimation value output; and a voltage-controlled oscillator for receiving said timing phase error estimation value output from said loop filter. and for applying a clock-generating signal to said A/D converter in accordance therewith.