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US5574946A Expired / Lapsed US ⏱️ 0.0 years remaining

Data transmission system using independent adaptation processes associated with storage unit types for directly converting operating system requests to SCSI commands

Assignee: Bull SAS
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Filing: 1996-02-20
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Granted: 1996-11-12
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Expires: 2016-02-20
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Abstract

Abstract A data transmission system between a computer bus and a large number of data storage units connected to one another by a specific connection to which the system is physically connected, including a central microprocessor running an operating system; and frame transfer capability including a data storage memory located between the bus and the connection. The operating system is associated with at least one application and includes at least one input/output microprocessor connected to the memory and to the connection. The application includes an initialization process; several adaptation processes each associated with a storage unit to adapt the protocols used on the buses and connection; and a task management process authorizing the input/output microprocessor to transfer the commands and the data corresponding to them from the memory to the connection and vice versa, on a message of the adaptation process.

Inventors

  • 👤 Patrick Sala

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 20:21
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; H; H04; H04L; H04L49/00; H04L49/90; H04L49/901; H04L49/9057

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 427 words
A data transmission system (MSP 1 , MSP 2 ) between a computer parallel bus (PSB) and a mass memory (SCSI 1 , SCSI 2 ) on a SCSI bus having a large number of data storage units (D 1 to D 5 , T 6 , D 7 to D 11 , T 12 ) connected to one another by a specific connection (BD 1 , BD 2 ) to which the system is physically connected, that includes a central microprocessor (CPU) connected to at least one memory (SRAM) containing an operating system (GPOS) designed to be executed by it comprising: means of transferring frames (MPC, B 2 , B 3 , VRAM, B 1 , DMAC, CTR 1 , CTR 2 ) between the computer bus and the connection, whose work is organized and managed by the microprocessor, including a data storage memory (VRAM) located between the computer bus and the connection; the operating system (GPOS) being associated with at least one specific application (A 1 , A 2 ) to transmit data between the computer bus (PSB) and said connection (BD 1 , BD 2 ); said data transmission system including at least one input/output microprocessor (CTR 1 , CTR 2 ) responsive to the central micro processor (CPU), connected to said data storage memory (VRAM) and to said connection; said at least one application including: a process for initialization (P 0 ) of an entire application, a plurality of separate adaptation processes independent from one another (P 1 to P 6 , P 7 to P 12 ), each of said adaptation processes associated with a certain type of storage unit, said processes directly converting commands sent via message semaphore from said GPOS into commands that comply with SCSI protocol, each said adaptation process communicating with one another by message semaphore to assist conversion, the conversion being carried out in the VRAM through correspondence tables located therein; and at least one management process authorizing the input/output microprocessor to transfer physically the commands and data in frames corresponding to them between the memory and the connection as soon as the corresponding adaptation process has finished said adaptation wherein the storage memory (VRAM) has second memory zones (BP 1 to BP 12 ), each assigned to storage of data intended for each of the different storage units, and tables (TP 1 to T 12 ) each associated with a certain one of them, including the address of the second memory zone associated with the same unit and the length of the necessary data stored there.
Claim 2
Dependent Claim 427 words
A data transmission system (MSP 1 , MSP 2 ) between a computer parallel bus (PSB) and a mass memory (SCSI 1 , SCSI 2 ) on a SCSI bus having a large number of data storage units (D 1 to D 5 , T 6 , D 7 to D 11 , T 12 ) connected to one another by a specific connection (BD 1 , BD 2 ) to which the system is physically connected, that includes a central microprocessor (CPU) connected to at least one memory (SRAM) containing an operating system (GPOS) designed to be executed by it comprising: means of transferring frames (MPC, B 2 , B 3 , VRAM, B 1 , DMAC, CTR 1 , CTR 2 ) between the computer bus and the connection, whose work is organized and managed by the microprocessor, including a data storage memory (VRAM) located between the computer bus and the connection; the operating system (GPOS) being associated with at least one specific application (A 1 , A 2 ) to transmit data between the computer bus (PSB) and said connection (BD 1 , BD 2 ); said data transmission system including at least one input/output microprocessor (CTR 1 , CTR 2 ) responsive to the central micro processor (CPU), connected to said data storage memory (VRAM) and to said connection; said at least one application including: a process for initialization (P 0 ) of an entire application, a plurality of separate adaptation processes independent from one another (P 1 to P 6 , P 7 to P 12 ), each of said adaptation processes associated with a certain type of storage unit, said processes directly converting commands sent via message semaphore from said GPOS into commands that comply with SCSI protocol, each said adaptation process communicating with one another by message semaphore to assist conversion, the conversion being carried out in the VRAM through correspondence tables located therein; and at least one management process authorizing the input/output microprocessor to transfer physically the commands and data in frames corresponding to them between the memory and the connection as soon as the corresponding adaptation process has finished said adaptation wherein the storage memory (VRAM) has second memory zones (BP 1 to BP 12 ), each assigned to storage of data intended for each of the different storage units, and tables (TP 1 to T 12 ) each associated with a certain one of them, including the address of the second memory zone associated with the same unit and the length of the necessary data stored there.
Claim 3
Dependent Claim 70 words
A data transmission system according to claim 1, wherein the plurality of adaptation processes (P 1 to P 6 , P 7 to P 12 ) and the management process (DR 1 , DR 2 ) are each associated with at least one message semaphore (SM 1 to SM 6 , SMD 1 ), and each of those processes can read into its associated semaphore and write into the others.
Claim 4
Dependent Claim 50 words
A system according to claim 2, further including at least one interrupt procedure (IT 1 , IT 2 ) configured to manage each of the interrupts generated by the input/output microprocessor (CTR 1 , CTR 2 ) at specific places in its input/output program (SP 1 to SP 12 ).
Claim 5
Dependent Claim 53 words
A system according to claim 2, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.
Claim 6
Dependent Claim 73 words
A system according to claim 2, wherein a data input/output program to or from the connection is associated with the input/output microprocessor, and is written, on one hand, into a special zone (SP) of the memory (SRAM) connected to the central processor, and, on the other hand, in said storage memory, as many times as there are adaptation processes, in initial memory zones reserves for that purpose (SP 1 to SP 12 ).
Claim 7
Dependent Claim 73 words
A system according to claim 5, wherein the storage memory (VRAM) has second memory zones (BP 1 to BP 12 ), each assigned to storage of data intended for each of the different storage units, and tables (TP 1 to TP 12 ) each associated with a certain one of them, including the address of the second memory zone associated with the same unit and the length of the necessary data stored there.
Claim 8
Dependent Claim 36 words
A system according to claim 6, wherein the contents of the table corresponding to the storage unit at work is recopied in a corresponding table (TP) in the memory (SRAM) associated with the central microprocessor (CPU).
Claim 9
Dependent Claim 53 words
A system according to claim 6, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.
Claim 10
Dependent Claim 53 words
A system according to claim 5, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.
Claim 11
Dependent Claim 36 words
A system according to claim 5, wherein the contents of the table corresponding to the storage unit at work is recopied in a corresponding table (TP) in the memory (SRAM) associated with the central microprocessor (CPU).
Claim 12
Dependent Claim 53 words
A system according to claim 10, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.
Claim 13
Dependent Claim 36 words
A system according to claim 11, wherein the contents of the table corresponding to the storage unit at work is recopied in a corresponding table (TP) in the memory (SRAM) associated with the central microprocessor (CPU).
Claim 14
Dependent Claim 53 words
A system according to claim 11, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.
Claim 15
Dependent Claim 73 words
A system according to claim 1, wherein a data input/output program to or from the connection is associated with the input/output microprocessor, and is written, on one hand, into a special zone (SP) of the memory (SRAM) connected to the central processor, and, on the other hand, in said storage memory, as many times as there are adaptation processes, in initial memory zones reserves for that purpose (SP 1 to SP 12 ).
Claim 16
Dependent Claim 73 words
A system according to claim 14, wherein the storage memory (VRAM) has second memory zones (BP 1 to BP 12 ), each assigned to storage of data intended for each of the different storage units, and tables (TP 1 to TP 12 ) each associated with a certain one of them, including the address of the second memory zone associated with the same unit and the length of the necessary data stored there.
Claim 17
Dependent Claim 36 words
A system according to claim 15, wherein the contents of the table corresponding to the storage unit at work is recopied in a corresponding table (TP) in the memory (SRAM) associated with the central microprocessor (CPU).
Claim 18
Dependent Claim 53 words
A system according to claim 15, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.
Claim 19
Dependent Claim 53 words
A system according to claim 14, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.
Claim 20
Dependent Claim 73 words
A system according to claim 1, wherein the storage memory (VRAM) has second memory zones (BP 1 to BP 12 ), each assigned to storage of data intended for each of the different storage units, and tables (TP 1 to TP 12 ) each associated with a certain one of them, including the address of the second memory zone associated with the same unit and the length of the necessary data stored there.
Claim 21
Dependent Claim 53 words
A system according to claim 19, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.
Claim 22
Dependent Claim 53 words
A system according to claim 1, wherein the memory associated with the central microprocessor has a list (LS) including a plurality of elements (E 1 to E 30 ), each defining a task executed by the input/output microprocessor for the transmission of data and corresponding commands to or from a certain storage unit.

References Cited (Backward Citations)

US4060849A Cited
US4965801A Cited
US5421014A Cited
US5293624A Cited
EP0481896A1 Cited
US5307491A Cited
US5257391A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-11-12 2000-05-13 2000-11-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-11-12 2004-05-13 2004-11-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-11-12 2008-05-13 2008-11-12 $7700.00 Window Closed / Lapsed

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