Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling

Claim 1

A method in a processor performed during handling of a first trap which occurs while executing a first instruction, the processor having a pipeline with a plurality of stages, a first indicator denoting an instruction which uses said pipeline, and a second indicator denoting whether to generate a trap on use of said pipeline, said method comprising the steps of: (a) saving said first indicator and said second indicator; (b) activating said second indicator and clearing said first indicator and continuing said handling of said first trap; (c) clearing said first indicator and said second indicator and saving said pipeline responsive to a second trap being generated during said handling of said first trap; (d) continuing said handling of said first trap; (e) restoring said first indicator and said second indicator; (f) restoring said pipeline; and (g) resuming execution at said first instruction.

Claim 2

A method in a processor performed during handling of a first trap which occurs while executing a first instruction, the processor having a pipeline with a plurality of stages, a first indicator denoting an instruction which uses said pipeline, and a second indicator denoting whether to generate a trap on use of said pipeline, said method comprising the steps of: (a) saving said first indicator and said second indicator; (b) activating said second indicator and clearing said first indicator and continuing said handling of said first trap; (c) clearing said first indicator and said second indicator and saving said pipeline responsive to a second trap being generated during said handling of said first trap; (d) continuing said handling of said first trap; (e) restoring said first indicator and said second indicator; (f) restoring said pipeline; and (g) resuming execution at said first instruction.

Claim 3

A method performed during handling of a trap generated by a first instruction in a processor having a pipeline and a means for indicating use of the pipeline by an instruction, the method comprising the steps of: (a) determining whether said means for indicating use of the pipeline is activated; (b) if said means for indicating use of the pipeline is activated, then saving a first state of said pipeline, otherwise continuing said handling of said trap absent said saving; (c) completing said handling of said trap; (d) if said means for indicating use of the pipeline was activated then restoring the pipeline to said first state, otherwise leaving said pipeline unmodified; and (e) resuming execution at said first instruction.

Claim 4

A method performed during handling of a trap generated by a first instruction in a processor having a pipeline and a means for indicating use of the pipeline by an instruction, the method comprising the steps of: (a) determining whether said means for indicating use of the pipeline is activated; (b) if said means for indicating use of the pipeline is activated, then saving a first state of said pipeline, otherwise continuing said handling of said trap absent said saving; (c) completing said handling of said trap; (d) if said means for indicating use of the pipeline was activated then restoring the pipeline to said first state, otherwise leaving said pipeline unmodified; and (e) resuming execution at said first instruction.

Claim 8

An apparatus comprising: a floating point unit which executes instructions in a pipeline; said pipeline having a plurality of pipeline stages; a processor status register having a plurality of bits, the plurality of bits including a first bit; and a trap handler for servicing traps, said trap handler also for saving the pipeline during servicing of a trap responsive to said first bit being in a first state, said trap handler for servicing the trap without saving the pipeline responsive to said first bit being in a second state.

Claim 9

An apparatus comprising: a floating point unit which executes instructions in a pipeline; said pipeline having a plurality of pipeline stages; a processor status register having a plurality of bits, the plurality of bits including a first bit; and a trap handler for servicing traps, said trap handler also for saving the pipeline during servicing of a trap responsive to said first bit being in a first state, said trap handler for servicing the trap without saving the pipeline responsive to said first bit being in a second state.

Claim 11

A method performed during trap handling in a processor, the processor having a pipeline comprising a plurality of stages, wherein instructions being executed by said processor are passed from stage to stage of said plurality of stages on consecutive clock cycles, said method comprising the steps of: (a) suspending execution at a first instruction and determining whether said first instruction is a pipeline instruction; (b) if said first instruction is the pipeline instruction, then saving a first state of said pipeline, otherwise continuing said trap handling absent said saving; (c) performing the trap handling; (d) if said first instruction is the pipeline instruction then restoring the pipeline to said first state, otherwise keeping said pipeline unmodified; and (e) resuming execution at said first instruction.

Claim 12

A method performed during trap handling in a processor, the processor having a pipeline comprising a plurality of stages, wherein instructions being executed by said processor are passed from stage to stage of said plurality of stages on consecutive clock cycles, said method comprising the steps of: (a) suspending execution at a first instruction and determining whether said first instruction is a pipeline instruction; (b) if said first instruction is the pipeline instruction, then saving a first state of said pipeline, otherwise continuing said trap handling absent said saving; (c) performing the trap handling; (d) if said first instruction is the pipeline instruction then restoring the pipeline to said first state, otherwise keeping said pipeline unmodified; and (e) resuming execution at said first instruction.

Claim 13

An apparatus comprising: a floating point unit which executes instructions in a pipeline, said pipeline having a plurality of pipeline stages; a processor status register having a plurality of bits, wherein a first bit of the plurality of bits has one of either a first state or a second state, said first state indicating that an instruction being executed uses the pipeline, said second state indicating that the instruction being executed does not use the pipeline; and a trap handler for servicing traps, said trap handler also for saving information in the plurality of pipeline stages during servicing of a trap responsive to said first bit being in said first state, said trap handler also for servicing the trap without saving the information in the plurality of pipeline stages responsive to said first bit being in said second state.

Claim 14

An apparatus comprising: a floating point unit which executes instructions in a pipeline, said pipeline having a plurality of pipeline stages; a processor status register having a plurality of bits, wherein a first bit of the plurality of bits has one of either a first state or a second state, said first state indicating that an instruction being executed uses the pipeline, said second state indicating that the instruction being executed does not use the pipeline; and a trap handler for servicing traps, said trap handler also for saving information in the plurality of pipeline stages during servicing of a trap responsive to said first bit being in said first state, said trap handler also for servicing the trap without saving the information in the plurality of pipeline stages responsive to said first bit being in said second state.

Claim 15

A method for handling a trap generated by an instruction in a processor, the method comprising the steps of: (a) checking whether a first bit in a processor status register is set; (b) saving both the first bit and a pipeline in the processor if the first bit is set, otherwise saving the first bit and not saving the pipeline if the first bit is not set; (c) completing handling of the trap; (d) restoring the first bit; and (e) restoring the pipeline if the pipeline was saved in the saving step (b), otherwise not restoring the pipeline.

Claim 16

A method for handling a trap generated by an instruction in a processor, the method comprising the steps of: (a) checking whether a first bit in a processor status register is set; (b) saving both the first bit and a pipeline in the processor if the first bit is set, otherwise saving the first bit and not saving the pipeline if the first bit is not set; (c) completing handling of the trap; (d) restoring the first bit; and (e) restoring the pipeline if the pipeline was saved in the saving step (b), otherwise not restoring the pipeline.

Claim 17

A method for handling a trap generated by an instruction in a processor, the method comprising the steps of: (a) saving a state of each bit of a plurality of bits in a processor status register; (b) setting a first bit of the plurality of bits and clearing a second bit of the plurality of bits; (c) saving a state of a pipeline in the processor responsive to the second bit becoming set due to continued handling of the trap, otherwise continuing handling of the trap without saving the state of the pipeline; (d) restoring the state of each bit of the plurality of bits; and (e) restoring the state of the pipeline if the state of the pipeline was saved in the saving step (c), otherwise not restoring the state of the pipeline.

Claim 18

A method for handling a trap generated by an instruction in a processor, the method comprising the steps of: (a) saving a state of each bit of a plurality of bits in a processor status register; (b) setting a first bit of the plurality of bits and clearing a second bit of the plurality of bits; (c) saving a state of a pipeline in the processor responsive to the second bit becoming set due to continued handling of the trap, otherwise continuing handling of the trap without saving the state of the pipeline; (d) restoring the state of each bit of the plurality of bits; and (e) restoring the state of the pipeline if the state of the pipeline was saved in the saving step (c), otherwise not restoring the state of the pipeline.

Claim 19

An apparatus comprising: a floating point unit which executes instructions in a pipeline, said pipeline having a plurality of pipeline stages; means for indicating an instruction which uses said pipeline; and means for indicating a trap is to occur if said pipeline is used.

Claim 20

An apparatus comprising: a floating point unit which executes instructions in a pipeline, said pipeline having a plurality of pipeline stages; means for indicating an instruction which uses said pipeline; and means for indicating a trap is to occur if said pipeline is used.