US5574864A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of implementing EISA bus devices on a host bus by disabling bridge circuitry between host and EISA buses
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-09-09
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Granted: 1996-11-12
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Expires: 2014-09-09
Abstract
Abstract In a computer system with a host bus and an EISA bus, devices typically implemented on an EISA bus are instead implemented on a host bus. These devices are still accessed with EISA commands, however, and an EISA bus controller bridge between the host bus and EISA bus is disabled on such accesses by being made to think that the actual command being executed on the host bus is a local memory command. This permits the EISA device to respond to EISA I/O and memory operations directed at addresses that it would normally respond to when connected to the EISA bus.
Inventors
- 👤 Theodore F. Emerson
- 👤 Timothy S. Wettach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:58
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
273 words
A computer system in which non-host bus devices are implemented on a host bus, comprising: a host bus; a microprocessor coupled to said host bus that executes memory operations and input/output operations on said host bus; a standard peripheral bus that includes an address space; bridge circuitry for communicating between said host bus and said standard peripheral bus, said bridge circuitry receiving a host bus memory access signal and a memory-input/output operation signal, wherein said bridge circuitry responds to an operation on said host bus by passing the operation to said standard peripheral bus when the operation is accompanied by the received memory-input/output operation signal indicating an input/output operation, but wherein said bridge circuitry is non-responsive to an operation on said host bus when the operation is accompanied by the received host bus memory access signal indicating a host bus memory access and the received memory-input/output operation signal indicating a memory operation; a device connected to said host bus, said device responsive to memory or input/output operations executed by said microprocessor directed to a predetermined portion of the address space of said standard peripheral bus; and means for disabling said bridge circuitry and enabling said device in response to memory or input/output operations directed to said predetermined portion of the address space, said means for disabling providing the memory-input/output operation signal and the host bus memory access signal to said bridge circuitry indicative of a memory operation and indicative of a host bus memory access, whereby said bridge circuitry is non-responsive on said host bus to memory or input/output operations on said host bus directed to said predetermined portion of the address space.
Claim 2
Dependent Claim
273 words
A computer system in which non-host bus devices are implemented on a host bus, comprising: a host bus; a microprocessor coupled to said host bus that executes memory operations and input/output operations on said host bus; a standard peripheral bus that includes an address space; bridge circuitry for communicating between said host bus and said standard peripheral bus, said bridge circuitry receiving a host bus memory access signal and a memory-input/output operation signal, wherein said bridge circuitry responds to an operation on said host bus by passing the operation to said standard peripheral bus when the operation is accompanied by the received memory-input/output operation signal indicating an input/output operation, but wherein said bridge circuitry is non-responsive to an operation on said host bus when the operation is accompanied by the received host bus memory access signal indicating a host bus memory access and the received memory-input/output operation signal indicating a memory operation; a device connected to said host bus, said device responsive to memory or input/output operations executed by said microprocessor directed to a predetermined portion of the address space of said standard peripheral bus; and means for disabling said bridge circuitry and enabling said device in response to memory or input/output operations directed to said predetermined portion of the address space, said means for disabling providing the memory-input/output operation signal and the host bus memory access signal to said bridge circuitry indicative of a memory operation and indicative of a host bus memory access, whereby said bridge circuitry is non-responsive on said host bus to memory or input/output operations on said host bus directed to said predetermined portion of the address space.
Claim 3
Dependent Claim
15 words
The computer system of claim 1, wherein said standard peripheral bus is an EISA bus.
Claim 4
Dependent Claim
29 words
The computer system of claim 2, wherein said predetermined portion of the address space includes input/output addresses 0zC80 hex to 0zC83 hex, where z equals 1 to 0F hex.
Claim 5
Dependent Claim
18 words
The computer system of claim 1, wherein said device connected to said host bus is a SCSI subsystem.
Claim 6
Dependent Claim
19 words
The computer system of claim 1, wherein said device connected to said host bus is a network interface controller.
Claim 7
Independent Claim
282 words
A method of implementing a non-host bus device on a host bus in a computer system with a microprocessor coupled to a host bus that executes memory operations and input/output operations on said host bus, a standard peripheral bus with an address space, and bridge circuitry linking the host bus to the standard peripheral bus, said bridge circuitry receiving a host bus memory access signal and a memory-input/output operation signal, wherein said bridge circuitry responds to an operation on said host bus by passing the operation to said standard peripheral bus when the operation is accompanied by the received memory-input/output operation signal indicating an input/output operation, but wherein said bridge circuitry is non-responsive to an operation on said host bus when the operation is accompanied by the received host bus memory access signal indicating a host bus memory access and the received memory-input/output operation signal indicating a memory operation, said method comprising the steps of: executing a memory or input/output operation directed to a predetermined portion of the address space of the standard peripheral bus to which the non-host bus device is responsive; determining that an operation on the host bus is a memory or input/output operation directed to the predetermined portion of the address space; disabling said bridge circuitry responsive to said determining step by providing the memory-input/output operation signal and the host bus memory access signal to said bridge circuitry indicative of a memory operation and indicative of a host bus memory access, whereby said bridge circuitry is non-responsive on the host bus to memory or input/output operations on the host bus directed to the predetermined portion of the address space; and enabling the device responsive to said determining step.
Claim 8
Independent Claim
282 words
A method of implementing a non-host bus device on a host bus in a computer system with a microprocessor coupled to a host bus that executes memory operations and input/output operations on said host bus, a standard peripheral bus with an address space, and bridge circuitry linking the host bus to the standard peripheral bus, said bridge circuitry receiving a host bus memory access signal and a memory-input/output operation signal, wherein said bridge circuitry responds to an operation on said host bus by passing the operation to said standard peripheral bus when the operation is accompanied by the received memory-input/output operation signal indicating an input/output operation, but wherein said bridge circuitry is non-responsive to an operation on said host bus when the operation is accompanied by the received host bus memory access signal indicating a host bus memory access and the received memory-input/output operation signal indicating a memory operation, said method comprising the steps of: executing a memory or input/output operation directed to a predetermined portion of the address space of the standard peripheral bus to which the non-host bus device is responsive; determining that an operation on the host bus is a memory or input/output operation directed to the predetermined portion of the address space; disabling said bridge circuitry responsive to said determining step by providing the memory-input/output operation signal and the host bus memory access signal to said bridge circuitry indicative of a memory operation and indicative of a host bus memory access, whereby said bridge circuitry is non-responsive on the host bus to memory or input/output operations on the host bus directed to the predetermined portion of the address space; and enabling the device responsive to said determining step.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |