US5572702A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
Assignee: Intel Corp
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Filing: 1994-02-28
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Granted: 1996-11-05
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Expires: 2014-02-28
Abstract
Abstract Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.
Inventors
- 👤 Nitin V. Sarangdhar
- 👤 Michael W. Rhodehamel
- 👤 Amit A. Merchant
- 👤 Matthew A. Fisch
- 👤 James M. Brayton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 02:51
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833; G06F13/00; G06F13/14; G06F13/16; G06F13/1668
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
202 words
A method of operating a computer system which includes a bus coupled to a memory unit, a first processor having a first cache, and a second processor having a second cache, said method comprising the steps of: (a) issuing a request as part of a pipelined transaction from said first processor to a target agent; (b) snooping said bus by said second processor to determine whether data corresponding to said request is contained in said second cache; (c) issuing one of either a first signal or a second signal by said second processor, said first signal indicating that said data is contained in said second cache in a modified state, and said second signal indicating that said data is contained in said second cache in an unmodified state; (d) placing said data from said second cache onto said bus to satisfy said request during said pipelined transaction, provided said first signal is issued; and (e) updating, based on which of said first signal or said second signal is issued in said step (c), a state of a cache line of said first cache corresponding to said data and a state of a cache line of said second cache corresponding to said data.
Claim 2
Independent Claim
202 words
A method of operating a computer system which includes a bus coupled to a memory unit, a first processor having a first cache, and a second processor having a second cache, said method comprising the steps of: (a) issuing a request as part of a pipelined transaction from said first processor to a target agent; (b) snooping said bus by said second processor to determine whether data corresponding to said request is contained in said second cache; (c) issuing one of either a first signal or a second signal by said second processor, said first signal indicating that said data is contained in said second cache in a modified state, and said second signal indicating that said data is contained in said second cache in an unmodified state; (d) placing said data from said second cache onto said bus to satisfy said request during said pipelined transaction, provided said first signal is issued; and (e) updating, based on which of said first signal or said second signal is issued in said step (c), a state of a cache line of said first cache corresponding to said data and a state of a cache line of said second cache corresponding to said data.
Claim 3
Dependent Claim
24 words
The method of claim 1 further comprising the step of latching said data from said second cache off said bus by said first processor.
Claim 4
Dependent Claim
24 words
The method of claim 1 further comprising the step of taking said data from said second cache off said bus by said target agent.
Claim 5
Dependent Claim
16 words
The method of claim 1 further comprising responding to said first processor from said target agent.
Claim 6
Independent Claim
13 words
The method of claim I wherein said target agent is said memory unit.
Claim 7
Independent Claim
15 words
The method of claim I wherein said request is an invalidation of cache line request.
Claim 8
Dependent Claim
30 words
The method of claim 5 wherein said request is a read request, said method further comprising taking said data from said second cache off said bus by said memory unit.
Claim 9
Dependent Claim
14 words
The method of claim 7 further comprising storing said data in said memory unit.
Claim 10
Dependent Claim
47 words
The method of claim 1 wherein said request is a write request, said method further comprising: placing write data corresponding to said write request on said bus by said first processor; and taking said write data off said bus by said memory unit and said second processor.
Claim 11
Dependent Claim
52 words
The method of claim 9 further comprising: taking said data from said second cache off said bus by said memory unit; creating an updated data unit by said memory unit by merging said write data and said data from said second cache; and storing said updated data unit in said memory unit.
Claim 12
Dependent Claim
23 words
The method of claim 9 wherein said write request is a write to a portion of said cache line of said second cache.
Claim 13
Independent Claim
240 words
A method of operating a computer system which includes a bus coupled to a requesting agent, said requesting agent having a first cache, a snooping agent having a second cache, and a memory unit, said method comprising the steps of: (a) issuing a read request as part of a pipelined transaction by said requesting agent, said read request having a target agent; (b) snooping said bus by said snooping agent to determine whether said read request can be satisfied by accessing data corresponding to said request contained in said second cache; (c) issuing one of either a first signal or a second signal from said snooping agent to said requesting agent indicating said read request can be satisfied by accessing said cache, said first signal indicating that said data is contained in said second cache in a modified state, and said second signal indicating that said data is contained in said second cache in an unmodified state; (d) placing said data from said second cache onto said bus during said pipelined transaction to satisfy said read request; (e) taking said data from said cache off said bus by said memory unit; and (f) updating, based on which of said first signal or said second signal is issued in said step (c), a state of a cache line of said first cache corresponding to said data and a state of a cache line of said second cache corresponding to said data.
Claim 14
Independent Claim
240 words
A method of operating a computer system which includes a bus coupled to a requesting agent, said requesting agent having a first cache, a snooping agent having a second cache, and a memory unit, said method comprising the steps of: (a) issuing a read request as part of a pipelined transaction by said requesting agent, said read request having a target agent; (b) snooping said bus by said snooping agent to determine whether said read request can be satisfied by accessing data corresponding to said request contained in said second cache; (c) issuing one of either a first signal or a second signal from said snooping agent to said requesting agent indicating said read request can be satisfied by accessing said cache, said first signal indicating that said data is contained in said second cache in a modified state, and said second signal indicating that said data is contained in said second cache in an unmodified state; (d) placing said data from said second cache onto said bus during said pipelined transaction to satisfy said read request; (e) taking said data from said cache off said bus by said memory unit; and (f) updating, based on which of said first signal or said second signal is issued in said step (c), a state of a cache line of said first cache corresponding to said data and a state of a cache line of said second cache corresponding to said data.
Claim 15
Dependent Claim
17 words
The method of claim 12 further comprising the step of storing said data in said memory unit.
Claim 16
Independent Claim
229 words
A method of operating a computer system which includes a bus coupled to a requesting processor having a first cache, a snooping processor having a second cache, and a memory unit, said method comprising the steps of: (a) issuing a write request as part of a pipelined transaction by said requesting processor, said write request having a target agent; (b) snooping on said bus by said snooping processor to determine whether first data corresponding to said write request is contained in said second cache; (c) issuing one of either a first signal or a second signal from said snooping processor to said requesting processor, said first signal indicating that said first data is contained in said second cache in a modified state, and said second signal indicating that said first data is contained in said second cache in an unmodified state; (d) placing second data corresponding to said write request on said bus by said requesting processor during said pipelined transaction; (e) taking said second data corresponding to said write request off said bus by said snooping processor; and (f) updating, based on which of said first signal or said second signal is issued in said step (c), a state of a cache line of said first cache corresponding to said second data and a state of a cache line of said second cache corresponding to said second data.
Claim 17
Independent Claim
229 words
A method of operating a computer system which includes a bus coupled to a requesting processor having a first cache, a snooping processor having a second cache, and a memory unit, said method comprising the steps of: (a) issuing a write request as part of a pipelined transaction by said requesting processor, said write request having a target agent; (b) snooping on said bus by said snooping processor to determine whether first data corresponding to said write request is contained in said second cache; (c) issuing one of either a first signal or a second signal from said snooping processor to said requesting processor, said first signal indicating that said first data is contained in said second cache in a modified state, and said second signal indicating that said first data is contained in said second cache in an unmodified state; (d) placing second data corresponding to said write request on said bus by said requesting processor during said pipelined transaction; (e) taking said second data corresponding to said write request off said bus by said snooping processor; and (f) updating, based on which of said first signal or said second signal is issued in said step (c), a state of a cache line of said first cache corresponding to said second data and a state of a cache line of said second cache corresponding to said second data.
Claim 18
Dependent Claim
34 words
The method of claim 14 further comprising the steps of: creating an updated data unit by merging said first data and said second data; and storing said updated data unit in said second cache.
Claim 19
Dependent Claim
23 words
The method of claim 15 wherein said write request is a write to a portion of said cache line of said second cache.
Claim 20
Dependent Claim
225 words
A computer system comprising: a pipelined bus coupled to a requesting agent, a snooping agent, and a memory unit, wherein said requesting agent is for issuing a request as part of a pipelined transaction having a target agent, wherein said requesting agent includes a first cache, and wherein said snooping agent includes a second cache; said snooping agent for, snooping on said bus in a first phase of said pipelined transaction to determine whether data corresponding to said request is contained in a cache line of said second cache, and issuing one of either a first signal or a second signal and placing data from said cache to satisfy said request onto said bus in a second phase of said pipelined transaction, wherein said first signal indicates that said data is contained in said second cache in a modified state, and said second signal indicates that said data is contained in said second cache in an unmodified state, and wherein said snooping agent is also for updating a state of said cache line of said second cache based on which of said first signal and said second signal issued; and wherein said requesting agent is also for updating a state of a cache line of said first cache corresponding to said data based on which of said first signal and said second signal is issued.
Claim 21
Dependent Claim
225 words
A computer system comprising: a pipelined bus coupled to a requesting agent, a snooping agent, and a memory unit, wherein said requesting agent is for issuing a request as part of a pipelined transaction having a target agent, wherein said requesting agent includes a first cache, and wherein said snooping agent includes a second cache; said snooping agent for, snooping on said bus in a first phase of said pipelined transaction to determine whether data corresponding to said request is contained in a cache line of said second cache, and issuing one of either a first signal or a second signal and placing data from said cache to satisfy said request onto said bus in a second phase of said pipelined transaction, wherein said first signal indicates that said data is contained in said second cache in a modified state, and said second signal indicates that said data is contained in said second cache in an unmodified state, and wherein said snooping agent is also for updating a state of said cache line of said second cache based on which of said first signal and said second signal issued; and wherein said requesting agent is also for updating a state of a cache line of said first cache corresponding to said data based on which of said first signal and said second signal is issued.
Claim 22
Dependent Claim
15 words
The system of claim 17 wherein said second phase is subsequent to said first phase.
Claim 23
Dependent Claim
25 words
The system of claim 17, wherein said memory unit is for taking said data from said second cache off said bus and storing said data.
Claim 24
Dependent Claim
49 words
The system of claim 17, wherein: said requesting agent is also for placing data corresponding to said request on said bus in a third phase of said pipelined transaction; and said memory unit is for taking said data corresponding to said request off said bus in said third phase.
Claim 25
Dependent Claim
38 words
The system of claim 20 wherein said memory unit is also for creating an updated data unit by merging said data corresponding to said request and said data from said second cache, and storing said updated data unit.
Claim 26
Dependent Claim
211 words
A computer system comprising: a pipelined bus; a first processor coupled to said bus, said first processor having a first cache memory.; a second processor coupled to said bus, said second cache memory processor having a second means for issuing a pipelined transaction on said bus from said first processor; means for snooping said bus to determine whether first data corresponding to said pipelined transaction is contained in said second cache memory, said means for snooping being coupled to said bus; means for issuing one of either a first signal or a second signal on said bus in a first phase of said pipelined transaction, said first signal indicating said first data is contained in said second cache memory in a modified state, and said second signal indicating said first data is contained in said second cache memory in an unmodified state; means for placing said first data onto said bus in a second phase of said pipelined transaction; and means for updating, based on whether said means for issuing issues said first signal or said second signal, a state of a cache line of said first cache memory corresponding to said first data and a state of a cache line of said second cache memory corresponding to said first data.
Claim 27
Dependent Claim
211 words
A computer system comprising: a pipelined bus; a first processor coupled to said bus, said first processor having a first cache memory.; a second processor coupled to said bus, said second cache memory processor having a second means for issuing a pipelined transaction on said bus from said first processor; means for snooping said bus to determine whether first data corresponding to said pipelined transaction is contained in said second cache memory, said means for snooping being coupled to said bus; means for issuing one of either a first signal or a second signal on said bus in a first phase of said pipelined transaction, said first signal indicating said first data is contained in said second cache memory in a modified state, and said second signal indicating said first data is contained in said second cache memory in an unmodified state; means for placing said first data onto said bus in a second phase of said pipelined transaction; and means for updating, based on whether said means for issuing issues said first signal or said second signal, a state of a cache line of said first cache memory corresponding to said first data and a state of a cache line of said second cache memory corresponding to said first data.
Claim 28
Dependent Claim
15 words
The system of claim 22 wherein said first phase is prior to said second phase.
Claim 29
Dependent Claim
25 words
The system of claim 22 further comprising means for placing second data corresponding to said pipelined transaction onto said bus prior to said first phase.
Claim 30
Dependent Claim
31 words
The system of claim 24 further comprising: means for creating an updated data unit by combining said first data and said second data; and means for storing said updated data unit.
Claim 31
Dependent Claim
259 words
A computer system comprising: a bus; a requesting processor coupled to said bus for issuing a write request in a first phase of a pipeline, said write request having a target agent, said requesting processor including a first cache memory; a memory unit coupled to said bus; a snooping agent coupled to said bus, wherein said snooping agent includes a second cache memory, and wherein said snooping agent is for, snooping on said bus in a second phase of said pipeline to determine whether data corresponding to said write request is contained in a cache line of said second cache memory, and issuing one of either a first signal or a second signal in said second phase and placing first data from said cache to satisfy said write request onto said bus in a third phase of said pipeline, wherein said first signal indicates that said first data is contained in said second cache memory in a modified state, and said second signal indicates that said first data is contained in said second cache memory in an unmodified state, and wherein said snooping agent is also for updating a state of a cache line of said second cache memory based on whether said first signal or said second signal is issued; wherein said requesting processor is also for updating a state of a cache line of said first cache memory based on whether said first signal or said second signal is issued; and said memory unit for taking said first data off said bus and storing said first data.
Claim 32
Dependent Claim
259 words
A computer system comprising: a bus; a requesting processor coupled to said bus for issuing a write request in a first phase of a pipeline, said write request having a target agent, said requesting processor including a first cache memory; a memory unit coupled to said bus; a snooping agent coupled to said bus, wherein said snooping agent includes a second cache memory, and wherein said snooping agent is for, snooping on said bus in a second phase of said pipeline to determine whether data corresponding to said write request is contained in a cache line of said second cache memory, and issuing one of either a first signal or a second signal in said second phase and placing first data from said cache to satisfy said write request onto said bus in a third phase of said pipeline, wherein said first signal indicates that said first data is contained in said second cache memory in a modified state, and said second signal indicates that said first data is contained in said second cache memory in an unmodified state, and wherein said snooping agent is also for updating a state of a cache line of said second cache memory based on whether said first signal or said second signal is issued; wherein said requesting processor is also for updating a state of a cache line of said first cache memory based on whether said first signal or said second signal is issued; and said memory unit for taking said first data off said bus and storing said first data.
Claim 33
Dependent Claim
45 words
The system of claim 26 wherein: said requesting processor is also for placing second data corresponding to said write request on said bus in said first phase; and said memory unit is also for taking said second data off said bus in said second phase.
Claim 34
Dependent Claim
32 words
The system of claim 27 wherein said memory unit is also for creating an updated data unit by merging said first data and said second data, and storing said updated data unit.
Claim 35
Dependent Claim
41 words
The method of claim 1, wherein said updating step (e) comprises the steps of: indicating said state of said cache line of said first cache is shared; and indicating said state of said cache line of said second cache is shared.
Claim 36
Dependent Claim
28 words
The method of claim 1, wherein said updating step (e) keeps both said cache line of said first cache and said cache line of said second cache valid.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |