US5572212A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pipelined analog to digital converter
Assignee: Exar Corp
•
Filing: 1995-03-31
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Granted: 1996-11-05
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Expires: 2015-03-31
Abstract
Abstract A pipelined analog to digital converter in which data samples ripple down through the pipeline of comparator stages. Each stage of the pipeline includes switch capacitor amplifiers for comparing an analog signal to a first reference voltage, to a second reference voltage, and to an average of the first and second reference voltages. Fan out of circuit components can be eliminated in succeeding stages, and error correction is provided by including overlapping of ranges passed by an earlier stage to a subsequent stage.
Inventors
- 👤 Roger A. Levinson
- 👤 Sang T. Ngo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:01
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/44; H03M1/442
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
148 words
A pipelined analog to digital converter comprising a plurality of pipelined analog comparator stages including a first stage, means for providing to said first stage an analog input signal (Ain), a first reference voltage (Vref1), and a second reference voltage (Vref2), said first stage having a first amplifier for providing an amplified comparison of said analog input signal and said first reference voltage ((Vref1-Ain) G), a second amplifier for providing an amplified comparison of said analog input signal and said second reference voltage, a middle reference generation circuit and amplifier for providing an amplified comparison of said analog input signal and an average of said first reference voltage and said second reference voltage ##EQU1## and latch means for storing a digital bit indicative of the amplified comparison of said analog input signal and said average, and multiplex means for transferring outputs of said amplifiers to a second stage.
Claim 2
Dependent Claim
148 words
A pipelined analog to digital converter comprising a plurality of pipelined analog comparator stages including a first stage, means for providing to said first stage an analog input signal (Ain), a first reference voltage (Vref1), and a second reference voltage (Vref2), said first stage having a first amplifier for providing an amplified comparison of said analog input signal and said first reference voltage ((Vref1-Ain) G), a second amplifier for providing an amplified comparison of said analog input signal and said second reference voltage, a middle reference generation circuit and amplifier for providing an amplified comparison of said analog input signal and an average of said first reference voltage and said second reference voltage ##EQU1## and latch means for storing a digital bit indicative of the amplified comparison of said analog input signal and said average, and multiplex means for transferring outputs of said amplifiers to a second stage.
Claim 3
Dependent Claim
18 words
The analog to digital converter as defined by claim 1 wherein each amplifier comprises a switched capacitor amplifier.
Claim 4
Dependent Claim
28 words
The analog to digital converter as defined by claim 2 wherein said multiplex means transfers outputs from said first stage as inputs to amplifiers in said second stage.
Claim 5
Dependent Claim
22 words
The analog to digital converter as defined by claim 3 wherein all amplifiers in said first stage have the same amplification factor.
Claim 6
Dependent Claim
31 words
The analog to digital converter as defined by claim 4 wherein all of said stages have the same number of inputs and outputs without fan out of components in succeeding stages.
Claim 7
Dependent Claim
22 words
The analog to digital converter as defined by claim 1 wherein all amplifiers in said first stage have the same amplification factor.
Claim 8
Dependent Claim
31 words
The analog to digital converter as defined by claim 6 wherein all of said stages have the same number of inputs and outputs without fan out of components in succeeding stages.
Claim 9
Dependent Claim
31 words
The analog to digital converter as defined by claim 1 wherein each succeeding stage receives a range from the preceding stage including an expected signal range and additional error correcting ranges.
Claim 10
Dependent Claim
18 words
The analog to digital converter as defined by claim 8 wherein a final stage includes a parallel conversion.
Claim 11
Dependent Claim
17 words
The analog to digital converter as defined by claim 8 wherein an intermediate stage includes error correction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |