US5570356A
Expired / Lapsed
US
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High bandwidth communications system having multiple serial links
Assignee: International Business Machines Corp
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Filing: 1995-06-07
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Granted: 1996-10-29
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Expires: 2015-06-07
Abstract
Abstract A data communication system includes a phase splitting circuit to split a high speed parallel data word into a number of individual parallel data bytes, a byte multiplexor for each of the phases of a phase splitting circuit, encoding and serialization circuits for converting each byte such as an 8-bit byte to an encoded form suitable for serial transmission such as by employing the Widmer et al. 8-bit/10-bit code, transmitting each encoded byte across one of a number of serial transmission links to a receiving device where the data is deserialized and decoded to recover the original byte which is then synchronized by a byte synchronization circuit. The byte synchronization circuits are then coupled to a word synchronization circuit where the original high bandwidth data word is recovered and transmitted on an internal high speed parallel bus within the receiving device.
Inventors
- 👤 Damon W. Finney
- 👤 Michael O. Jenkins
- 👤 Michael J. Rayfield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:47
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
169 words
A data communications system, comprising: first circuit means for dividing an input data signal into a plurality of phases; a plurality of second circuit means for multiplexing a plurality of bytes from each phase; a plurality of parallel to serial converting circuits, one of said parallel to serial converting circuits associated with each of said phases, for converting each parallel byte to serial form for transmission on one of a plurality of serial transmission media; a plurality of serial transmission media; a plurality of serial to parallel converter circuits, each connected to one of said plurality of said serial transmission media for converting the serial data streams to parallel form; a plurality of byte synchronization circuits for placing a plurality of bytes for each phase in correct order; and a word synchronization circuit having inputs connected to each of said byte synchronization circuits for assembling said plurality of bytes for each phase into a word and for transmitting each said word to a parallel data bus in synchronized order.
Claim 2
Dependent Claim
169 words
A data communications system, comprising: first circuit means for dividing an input data signal into a plurality of phases; a plurality of second circuit means for multiplexing a plurality of bytes from each phase; a plurality of parallel to serial converting circuits, one of said parallel to serial converting circuits associated with each of said phases, for converting each parallel byte to serial form for transmission on one of a plurality of serial transmission media; a plurality of serial transmission media; a plurality of serial to parallel converter circuits, each connected to one of said plurality of said serial transmission media for converting the serial data streams to parallel form; a plurality of byte synchronization circuits for placing a plurality of bytes for each phase in correct order; and a word synchronization circuit having inputs connected to each of said byte synchronization circuits for assembling said plurality of bytes for each phase into a word and for transmitting each said word to a parallel data bus in synchronized order.
Claim 3
Dependent Claim
29 words
A data communication system, according to claim 1, further comprising: an encoder circuit for encoding said plurality of bytes from each phase into a form suitable for error protection.
Claim 4
Dependent Claim
37 words
A data communication system, according to claim 2, further comprising: a plurality of decoder circuits, each connected to an output of one of said serial to parallel converting circuits for converting said encoded data to original form.
Claim 5
Independent Claim
97 words
A method of transmitting data at an improved bandwidth in a data communication system, comprising the steps of: dividing an input data signal into a plurality of phases; multiplexing a plurality of bytes from each phase; converting each byte to serial form for transmission on one of a plurality of serial transmission media; converting the serial form of each byte to parallel form; placing a plurality of bytes for each phase in correct order; assembling the plurality of bytes for each phase into a word; and transmitting each word to a parallel data bus in synchronized order.
Claim 6
Independent Claim
97 words
A method of transmitting data at an improved bandwidth in a data communication system, comprising the steps of: dividing an input data signal into a plurality of phases; multiplexing a plurality of bytes from each phase; converting each byte to serial form for transmission on one of a plurality of serial transmission media; converting the serial form of each byte to parallel form; placing a plurality of bytes for each phase in correct order; assembling the plurality of bytes for each phase into a word; and transmitting each word to a parallel data bus in synchronized order.
Claim 7
Dependent Claim
38 words
A method of transmitting data at an improved bandwidth in a data communication system according to claim 4, further comprising the step of: encoding the plurality of bytes from each phase into a form suitable for error protection.
Claim 8
Dependent Claim
30 words
A method of transmitting data at an improved bandwidth in a data communication system according to claim 5, further comprising the step of: converting said encoded data to original form.
Claim 9
Dependent Claim
67 words
A data transmission system, comprising: first circuit means for dividing an input data signal into a plurality of phases; a plurality of second circuit means for multiplexing a plurality of bytes from each phase; and a plurality of parallel to serial converting circuits, one of said parallel to serial converting circuits associated with each of said phases, for converting each parallel byte to serial form for transmission.
Claim 10
Dependent Claim
67 words
A data transmission system, comprising: first circuit means for dividing an input data signal into a plurality of phases; a plurality of second circuit means for multiplexing a plurality of bytes from each phase; and a plurality of parallel to serial converting circuits, one of said parallel to serial converting circuits associated with each of said phases, for converting each parallel byte to serial form for transmission.
Claim 11
Dependent Claim
29 words
A data transmission system, according to claim 7, further comprising: an encoder circuit for encoding each byte of said input data signal into a form suitable for error protection.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |