High density integrated circuit assembly combining leadframe leads with conductive traces

Claim 2

An integrated circuit assembly, comprising: a) a dielectric substrate defining a predetermined array of electrically conductive traces on a first surface thereof; b) a plurality of leadframe leads supported by said substrate and electrically isolated from said traces; c) an IC chip supported by the substrate on the first surface, said IC chip including a series of input/output pads; and d) a first series of bonding wires respectively electrically connecting certain ones of the input/output pads of the IC chip to respective ones of said traces and a second series of bonding wires respectively electrically connecting certain other ones of the input/output pads of the IC chip to respective ones of said leadframe leads, whereby the IC chip can be connected to external components in a predetermined way through both said electrically conductive traces and said leadframe leads e) said substrate further including at least said first surface and a second opposing surface, said first surface supporting said IC chip and said leadframe leads, said substrate further including a plurality of elongated, electrically conductive members attached to said second surface in predetermined positions, and wherein said conductive traces extend from said first surface to said second surface, each of said traces being electrically connected to an associated one of said elongated members.

Claim 3

An integrated circuit assembly according to claim 1 wherein said elongated members are attached to said second surface in a predetermined grid array.

Claim 4

An integrated circuit assembly according to claim 1 wherein each of said elongated members is a solder column.

Claim 5

An integrated circuit assembly according to claim 1 wherein each of said elongated members is an attachment pin.

Claim 6

An integrated circuit assembly, comprising: a) a dielectric substrate including a predetermined array of electrically conductive traces, said substrate further including opposing first and second surfaces such that said conductive traces extend from the first surface to the second surface, said substrate still further including a plurality of elongated members attached to said second surface in predetermined positions such that each member is electrically connected to a respective one of said conductive traces; b) a plurality of leadframe leads supported by said first surface of said substrate such that at least some of said leadframe leads overlie said conductive traces; c) an IC chip supported on the first surface of said substrate and including a series of input/output pads, at least one power terminal and at least one ground terminal; d) a first series of bonding wires respectively electrically connecting certain ones of said input/output pads of the IC chip to respective ones of said traces on said first surface and a second series of bonding wires respectively electrically connecting certain other ones of the input/output pads of the IC chip to respective ones of said leadframe leads on said first surface; e) first and second electrically conductive layers positioned in a stacked relationship with respect to one another on said substrate and overlying at least some of said leadframe leads, said layers selectively serving as power or ground planes, respectively; f) means for electrically insulating said layers from one another and from said leadframe leads therebelow; and g) means for electrically connecting said first and second layers to specific ones of said leadframe leads or conductive traces and further electrically connecting said first and second layers to respective power and ground terminals on said IC chip, whereby to provide preselectable power and ground planes for electrical interconnection of the IC chip.

Claim 7

An integrated circuit assembly, comprising: a) a dielectric substrate including a predetermined array of electrically conductive traces, said substrate further including opposing first and second surfaces such that said conductive traces extend from the first surface to the second surface, said substrate still further including a plurality of elongated members attached to said second surface in predetermined positions such that each member is electrically connected to a respective one of said conductive traces; b) a plurality of leadframe leads supported by said first surface of said substrate such that at least some of said leadframe leads overlie said conductive traces; c) an IC chip supported on the first surface of said substrate and including a series of input/output pads, at least one power terminal and at least one ground terminal; d) a first series of bonding wires respectively electrically connecting certain ones of said input/output pads of the IC chip to respective ones of said traces on said first surface and a second series of bonding wires respectively electrically connecting certain other ones of the input/output pads of the IC chip to respective ones of said leadframe leads on said first surface; e) first and second electrically conductive layers positioned in a stacked relationship with respect to one another on said substrate and overlying at least some of said leadframe leads, said layers selectively serving as power or ground planes, respectively; f) means for electrically insulating said layers from one another and from said leadframe leads therebelow; and g) means for electrically connecting said first and second layers to specific ones of said leadframe leads or conductive traces and further electrically connecting said first and second layers to respective power and ground terminals on said IC chip, whereby to provide preselectable power and ground planes for electrical interconnection of the IC chip.

Claim 8

An integrated circuit assembly according to claim 5 wherein each of elongated members is a solder column.

Claim 9

An integrated circuit assembly according to claim 6 wherein each of said elongated members is an attachment pin.

Claim 10

An integrated circuit assembly, comprising; a) a dielectric substrate including a predetermined array of electrically conductive traces, said substrate further including opposing first and second surfaces such that said conductive traces extend from the first surface to the second surface, said substrate still further including a plurality of elongated members attached to said second surface in predetermined positions such that each elongated member is electrically connected to a respective one of said conductive traces; b) a plurality of leadframe leads supported by said first surface of said substrate such that at least some of said leadframe leads overlie said conductive traces; c) an IC chip supported on the first surface of said substrate and including a series of input/output pads, at least one power terminal and at least one ground terminal; d) a first array of bonding wires respectively electrically connecting certain ones of the input/output pads of the IC chip to respective ones of said traces on said first surface and a second array of bonding wires respectively electrically connecting certain other ones of the input/output pads of the IC chip to respective ones of said leadframe leads on said first surface, whereby to externally electrically connect the IC chip in a predetermined way; e) first and second electrically conductive layers positioned in a stacked relationship with respect to one another on said substrate and overlying at least some of said leadframe leads, said layers selectively serving as power or ground planes, respectively; f) a dielectric material electrically insulating said first and second layers from one another and from said leadframe leads therebelow, wherein said dielectric material serves to bond said layers to one another and to the substrate; g) a first series of bonding wires electrically connecting said first and second layers to specific ones of said leadframe leads or conductive traces, and a second series of bonding wires electrically connecting said first and second layers to respective preselected power or ground terminals on said IC chip, whereby to provide preselectable power or ground planes for electrical interconnection of the IC chip; and h) a dielectric material encapsulating at least a portion of said integrated circuit assembly.

Claim 11

An integrated circuit assembly, comprising; a) a dielectric substrate including a predetermined array of electrically conductive traces, said substrate further including opposing first and second surfaces such that said conductive traces extend from the first surface to the second surface, said substrate still further including a plurality of elongated members attached to said second surface in predetermined positions such that each elongated member is electrically connected to a respective one of said conductive traces; b) a plurality of leadframe leads supported by said first surface of said substrate such that at least some of said leadframe leads overlie said conductive traces; c) an IC chip supported on the first surface of said substrate and including a series of input/output pads, at least one power terminal and at least one ground terminal; d) a first array of bonding wires respectively electrically connecting certain ones of the input/output pads of the IC chip to respective ones of said traces on said first surface and a second array of bonding wires respectively electrically connecting certain other ones of the input/output pads of the IC chip to respective ones of said leadframe leads on said first surface, whereby to externally electrically connect the IC chip in a predetermined way; e) first and second electrically conductive layers positioned in a stacked relationship with respect to one another on said substrate and overlying at least some of said leadframe leads, said layers selectively serving as power or ground planes, respectively; f) a dielectric material electrically insulating said first and second layers from one another and from said leadframe leads therebelow, wherein said dielectric material serves to bond said layers to one another and to the substrate; g) a first series of bonding wires electrically connecting said first and second layers to specific ones of said leadframe leads or conductive traces, and a second series of bonding wires electrically connecting said first and second layers to respective preselected power or ground terminals on said IC chip, whereby to provide preselectable power or ground planes for electrical interconnection of the IC chip; and h) a dielectric material encapsulating at least a portion of said integrated circuit assembly.

Claim 12

An integrated circuit assembly according to claim 9 wherein each of said elongated members is a solder column.

Claim 13

An integrated circuit assembly according to claim 9 wherein each of said elongated members is an attachment pin.

Claim 14

An integrated circuit assembly comprising: a) a dielectric substrate including a predetermined array of electrically conductive traces, said substrate further including opposing first and second surfaces such that said conductive traces extend from the first surface to the second surface, said substrate still further including a plurality of elongated members attached to said second surface in a grid array such that each member is electrically connected to a respective one of said conductive traces; b) a plurality of leadframe leads supported by said first surface of said substrate such that at least some of said leadframe leads overlie said conductive traces; c) an IC chip supported on the first surface of said substrate, said IC chip including a series of input/output pads and still further including additional electrical terminals; d) a first array of bonding wires respectively electrically connecting certain ones of the input/output pads of the IC chip to respective ones of said traces on said first surface and a second array of bonding wires respectively electrically connecting certain other ones of the input/output pads of the IC chip to respective ones of said leadframe leads on said first surface; e) first and second electrically conductive layers positioned in a stacked relationship with respect to one another on said substrate and overlying at least some of said leadframe leads, said layers selectively serving as conductive planes for preselectable electrical connection respectively to said IC chip in accordance with a predetermined circuit design; f) a dielectric material electrically insulating said first and second layers from one another and from said leadframe leads there below such that said dielectric material serves to bond said layers to one another and to the substrate; g) a first series of bonding wires electrically connecting said first and second layers to specific ones of said leadframe leads or conductive traces, and a second series of bonding wires electrically connecting said first and second layers to said additional terminals on the IC chip, whereby to provide preselectable electrical interconnection of the IC chip; and h) a dielectric material encapsulating at least a portion of said integrated circuit assembly.

Claim 15

An integrated circuit assembly comprising: a) a dielectric substrate including a predetermined array of electrically conductive traces, said substrate further including opposing first and second surfaces such that said conductive traces extend from the first surface to the second surface, said substrate still further including a plurality of elongated members attached to said second surface in a grid array such that each member is electrically connected to a respective one of said conductive traces; b) a plurality of leadframe leads supported by said first surface of said substrate such that at least some of said leadframe leads overlie said conductive traces; c) an IC chip supported on the first surface of said substrate, said IC chip including a series of input/output pads and still further including additional electrical terminals; d) a first array of bonding wires respectively electrically connecting certain ones of the input/output pads of the IC chip to respective ones of said traces on said first surface and a second array of bonding wires respectively electrically connecting certain other ones of the input/output pads of the IC chip to respective ones of said leadframe leads on said first surface; e) first and second electrically conductive layers positioned in a stacked relationship with respect to one another on said substrate and overlying at least some of said leadframe leads, said layers selectively serving as conductive planes for preselectable electrical connection respectively to said IC chip in accordance with a predetermined circuit design; f) a dielectric material electrically insulating said first and second layers from one another and from said leadframe leads there below such that said dielectric material serves to bond said layers to one another and to the substrate; g) a first series of bonding wires electrically connecting said first and second layers to specific ones of said leadframe leads or conductive traces, and a second series of bonding wires electrically connecting said first and second layers to said additional terminals on the IC chip, whereby to provide preselectable electrical interconnection of the IC chip; and h) a dielectric material encapsulating at least a portion of said integrated circuit assembly.

Claim 16

An integrated circuit assembly according to claim 11 wherein each of said elongated members is a solder column.

Claim 17

An integrated circuit assembly according to claim 12 wherein each of said elongated members is an attachment pin.