US5568637A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic device having pseudo-SRAM and CPU operating in an active mode and in an idle mode
Assignee: Intellectual Ventures Holding 81 LLC
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Filing: 1994-06-20
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Granted: 1996-10-22
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Expires: 2014-06-20
Abstract
Abstract An electronic device uses a pseudo-SRAM having a self-refreshing function, as a memory, and a refresh timing signal having a predetermined period is supplied to the pseudo-SRAM in the operation state of the electronic device. When no key operation is performed with a keyboard for a predetermined period of time, the electronic device switches into an idle mode to stop supply of an operation clock to a CPU and to stop supply of the timing signal to the pseudo-SRAM. When the supply of the timing signal to the pseudo-SRAM is stopped, the pseudo-SRAM operates the self-refreshing function for holding data with low power consumption. When a key operation is detected in the idle mode, a refresh timing signal having a high frequency is supplied to the pseudo-SRAM for a predetermined period of time. Thereafter, the supply of a clock to the CPU is restarted, and the state of the electronic device is returned to a normal operation state.
Inventors
- 👤 Kouji Moriya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:23
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/02; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
166 words
An electronic device comprising: a CPU which controls an operation of said electronic device, said CPU functioning in an active mode in which said CPU operates and in an idle mode in which said CPU does not operate; a pseudo-SRAM connected to said CPU and having a self-refreshing function; storage means for storing data denoting the active mode in which said CPU operates and the idle mode in which said CPU does not operate; refresh signal supplying means for supplying a first refresh timing signal of a predetermined period to cause said pseudo-SRAM to perform an automatic refreshing operation when said CPU is in the active mode, for stopping supply of the first refresh timing signal when said CPU is in the idle mode, and for supplying, when the idle mode of said CPU is switched to the active mode of said CPU, a second refresh timing signal having a period shorter than that of the first refresh timing signal for a predetermined interval of time.
Claim 2
Dependent Claim
166 words
An electronic device comprising: a CPU which controls an operation of said electronic device, said CPU functioning in an active mode in which said CPU operates and in an idle mode in which said CPU does not operate; a pseudo-SRAM connected to said CPU and having a self-refreshing function; storage means for storing data denoting the active mode in which said CPU operates and the idle mode in which said CPU does not operate; refresh signal supplying means for supplying a first refresh timing signal of a predetermined period to cause said pseudo-SRAM to perform an automatic refreshing operation when said CPU is in the active mode, for stopping supply of the first refresh timing signal when said CPU is in the idle mode, and for supplying, when the idle mode of said CPU is switched to the active mode of said CPU, a second refresh timing signal having a period shorter than that of the first refresh timing signal for a predetermined interval of time.
Claim 3
Dependent Claim
47 words
A device according to claim 1, wherein an operation clock is supplied to said CPU when said CPU is in the active mode, and said device further comprises means for stopping supply of the operation clock to said CPU when said CPU is in the idle mode.
Claim 4
Dependent Claim
80 words
A device according to claim 2, further comprising: key input means for performing a key operation; detection means for detecting that no key input operation is performed by said key input means for a predetermined period of time; and means for switching a mode of operation of said CPU from the active mode to the idle mode when said detection means detects that no key input operation is performed by said key input means for the predetermined period of time.
Claim 5
Dependent Claim
83 words
A device according to claim 3, wherein: said detection means includes means for detecting that a key input operation of said key input means is performed when said CPU is in the idle mode; and said means for switching includes means for switching a mode of operation of said CPU from the idle mode to the active mode when said detection means detects that a key input operation of said key input means is performed when said CPU is in the idle mode.
Claim 6
Dependent Claim
52 words
A device according to claim 1, wherein said refresh signal supplying means comprises: a first signal generation circuit which generates the first refresh timing signal; a second signal generation circuit which generates the second refresh timing signal; and a switching circuit which controls transfer of the first and second refresh timing signals.
Claim 7
Dependent Claim
51 words
A device according to claim 5, wherein: said refresh signal supplying means further comprises a counter for counting pulses of the second refresh timing signal; and said switching circuit comprises means for switching from the second to the first refresh timing signal upon count-up of said counter to a predetermined number.
Claim 8
Dependent Claim
144 words
An electronic device comprising: key input unit; a CPU for performing a process corresponding to a key operation of said key input unit; a pseudo-SRAM having a self-refreshing function; detection means for detecting a presence of performance of a key operation on said key input unit; and refresh timing signal control means for supplying a first refresh timing signal having a predetermined period to said pseudo-SRAM in an operation state of said CPU, for stopping supply of the first refresh timing signal when no key operation on said key input unit is detected by said detection means for a predetermined period of time, and for supplying a second refresh timing signal having a period shorter than that of the first refresh timing signal for an interval of time, when said detection means detects a presence of a key operation on said key input unit.
Claim 9
Dependent Claim
144 words
An electronic device comprising: key input unit; a CPU for performing a process corresponding to a key operation of said key input unit; a pseudo-SRAM having a self-refreshing function; detection means for detecting a presence of performance of a key operation on said key input unit; and refresh timing signal control means for supplying a first refresh timing signal having a predetermined period to said pseudo-SRAM in an operation state of said CPU, for stopping supply of the first refresh timing signal when no key operation on said key input unit is detected by said detection means for a predetermined period of time, and for supplying a second refresh timing signal having a period shorter than that of the first refresh timing signal for an interval of time, when said detection means detects a presence of a key operation on said key input unit.
Claim 10
Dependent Claim
31 words
A device according to claim 7, further comprising: first signal generation means for generating the first refresh timing signal; and second signal generation means for generating the second refresh timing signal.
Claim 11
Dependent Claim
54 words
A device according to claim 8, wherein said refresh timing signal control means further comprises: a counter for counting the number of timing signals generated by said second signal generation means; and a switching circuit for switching from the second to the first timing signal when said counter counts up to a predetermined number.
Claim 12
Dependent Claim
45 words
A device according to claim 9, further comprising: means for storing operation modes of said electronic device, the operation modes including an active mode in which said CPU is operated to perform a process and an idle mode in which said CPU is not operated.
Claim 13
Dependent Claim
55 words
A device according to claim 10, further comprising: means for switching a mode of operation of said CPU from the active mode of said CPU to the idle mode of said CPU, when said detection means detects that no key input operation is performed by said key input unit for the predetermined period of time.
Claim 14
Dependent Claim
48 words
A device according to claim 7, wherein an operation clock is supplied to said CPU, and said device further comprises means for stopping supply of the first refresh timing signal and stopping supply of the operation clock to said CPU when said CPU is not performing a process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |