Method and device for transferring data in a TDMA system

Claim 1

A device for transferring data between a plurality of digital signal processors in a system utilizing time division multiple access, said device comprising: a system controller coupled to a bus network; a plurality of dual port random access memory devices, each of which has a first port coupled to one of said plurality of digital signal processors and a second port coupled to said bus network; and a linked list direct memory access controller for transferring data between said dual port random access memory devices, said direct memory access controller coupled to said bus network and controlled by said system controller; said system controller further comprising a timing generation circuit for generating a first periodic signal, said first periodic signal being coupled to each of said plurality of digital signal processors and said memory access controller, said first periodic signal defining the start of said first predefined time period; and a delay circuit for delaying said first periodic signal a predetermined amount so as to create a start signal defining the beginning of said second predefined time period, said start signal being coupled to said memory controller.

Claim 2

A device for transferring data between a plurality of digital signal processors in a system utilizing time division multiple access, said device comprising: a system controller coupled to a bus network; a plurality of dual port random access memory devices, each of which has a first port coupled to one of said plurality of digital signal processors and a second port coupled to said bus network; and a linked list direct memory access controller for transferring data between said dual port random access memory devices, said direct memory access controller coupled to said bus network and controlled by said system controller; said system controller further comprising a timing generation circuit for generating a first periodic signal, said first periodic signal being coupled to each of said plurality of digital signal processors and said memory access controller, said first periodic signal defining the start of said first predefined time period; and a delay circuit for delaying said first periodic signal a predetermined amount so as to create a start signal defining the beginning of said second predefined time period, said start signal being coupled to said memory controller.

Claim 8

A method for transferring data between a plurality of digital signal processors in a system utilizing time division multiple access, comprising: allocating by a system controller a first predefined time period within a TDMA cycle in which each of said plurality of digital signal processors access a dual port random access memory device coupled thereto, allocating by the system controller a second predefined time period within said TDMA cycle in which a linked list direct memory access controller transfers data between said dual port random access memory devices, and allocating by the system controller a third predefined time period within said TDMA cycle in which the system controller accesses said dual port random access memory devices coupled to said plurality of digital signal processors.

Claim 9

A method for transferring data between a plurality of digital signal processors in a system utilizing time division multiple access, comprising: allocating by a system controller a first predefined time period within a TDMA cycle in which each of said plurality of digital signal processors access a dual port random access memory device coupled thereto, allocating by the system controller a second predefined time period within said TDMA cycle in which a linked list direct memory access controller transfers data between said dual port random access memory devices, and allocating by the system controller a third predefined time period within said TDMA cycle in which the system controller accesses said dual port random access memory devices coupled to said plurality of digital signal processors.

Claim 18

A device for transferring data between a plurality of digital signal processors in a time division multiple access system, said device comprising: a bus network; a system controller coupled to said bus network, said system controller further comprising a timing generation circuit for generating a first periodic signal, said first periodic signal being said to each of said plurality of digital signal processors, said first periodic signal defining the start of a first predefined time period; a plurality of random access memory devices, each of which is coupled to one of said plurality of digital signal processors and to said bus network; a memory controller for transferring data between said random access memory devices, said memory controller coupled to said bus network and controlled by said system controller; a delay circuit for delaying said first periodic signal for a predetermined amount of time so as to create a start signal defining the beginning of a second predefined time period, said start signal being coupled to said memory controller; and a timing bus coupled between said timing generation circuit, said delay circuit and said plurality of digital signal processors so as to allow said first periodic signal to be transmitted to said plurality of digital signal processors and said memory controller.

Claim 19

A device for transferring data between a plurality of digital signal processors in a time division multiple access system, said device comprising: a bus network; a system controller coupled to said bus network, said system controller further comprising a timing generation circuit for generating a first periodic signal, said first periodic signal being said to each of said plurality of digital signal processors, said first periodic signal defining the start of a first predefined time period; a plurality of random access memory devices, each of which is coupled to one of said plurality of digital signal processors and to said bus network; a memory controller for transferring data between said random access memory devices, said memory controller coupled to said bus network and controlled by said system controller; a delay circuit for delaying said first periodic signal for a predetermined amount of time so as to create a start signal defining the beginning of a second predefined time period, said start signal being coupled to said memory controller; and a timing bus coupled between said timing generation circuit, said delay circuit and said plurality of digital signal processors so as to allow said first periodic signal to be transmitted to said plurality of digital signal processors and said memory controller.

Claim 22

An apparatus for receiving a plurality of telephone signals carried by a plurality of telephone lines and generating a concentrated telephone signal to be transmitted by an antenna over a radio communication link comprising: a telephone line circuit module receiving the plurality of telephone lines and producing the plurality of respective telephone signals; a first digital signal processor comprising an encoder receiving the plurality of telephone signals from the telephone line circuit and producing encoded telephone signals; a system controller coupled to a bus network, said system controller receiving the encoded telephone signals and generating a concentrated telephone signal having a plurality of speech slots, each of the encoded telephone signals assigned to at least one of the speech slots; a second digital signal processor comprising a modem responsive to said system controller, said modem modulating said concentrated telephone signal to produce a modulated signal; a plurality of dual port random access memory devices, each of which has a first port coupled to said digital signal processors and a second port coupled to said bus network; a memory controller for transferring data between said dual port random access memory devices, said memory controller coupled to said bus network and controlled by said system controller; and a transceiving module coupled to the antenna and responsive to said modem, said transceiving module transmitting said modulated signal over the radio communication link via the antenna.

Claim 23

An apparatus for receiving a plurality of telephone signals carried by a plurality of telephone lines and generating a concentrated telephone signal to be transmitted by an antenna over a radio communication link comprising: a telephone line circuit module receiving the plurality of telephone lines and producing the plurality of respective telephone signals; a first digital signal processor comprising an encoder receiving the plurality of telephone signals from the telephone line circuit and producing encoded telephone signals; a system controller coupled to a bus network, said system controller receiving the encoded telephone signals and generating a concentrated telephone signal having a plurality of speech slots, each of the encoded telephone signals assigned to at least one of the speech slots; a second digital signal processor comprising a modem responsive to said system controller, said modem modulating said concentrated telephone signal to produce a modulated signal; a plurality of dual port random access memory devices, each of which has a first port coupled to said digital signal processors and a second port coupled to said bus network; a memory controller for transferring data between said dual port random access memory devices, said memory controller coupled to said bus network and controlled by said system controller; and a transceiving module coupled to the antenna and responsive to said modem, said transceiving module transmitting said modulated signal over the radio communication link via the antenna.