Self timed address locking and data latching circuit

Claim 2

A data and address control circuit, comprising; a row address strobe line; a column address strobe line; an inverse read line; a data latch enable line; an address lock enable line; a timing control circuit having a first input, a second input, a third input and an output wherein said first input of said timing control circuit is connected to said column address strobe line, said second input of said timing control circuit is connected to said row address strobe line, said third input of said timing control circuit is connected to said inverse read line, said output of said timing control circuit is at a logical zero level when said row address strobe line is at a logical zero level or said column address strobe line is at a logical one level, and said output of said timing control circuit is at a logical one level when said row address strobe line is at a logical one level, said inverse read line is at a logical zero level, and said column address strobe line has switched from a logical one level to a logical zero level; an address lock circuit having a first input, a second input, and an output wherein said first input of said address lock circuit is connected to said column address strobe line, said second input of said address lock circuit is connected to said address lock enable line, said output of said address lock circuit is at a logical one level if said column address strobe line is at a logical one level, said output of said address lock circuit is at a logical one level if said address lock enable line is at a logical one level and said output of said timing control circuit is at a logical one level; and a data latch circuit having a first input, a second input, and an output wherein said first input is connected to said data latch enable line, said second input is connected to said output of said timing control circuit and to said output of said address lock circuit, said output of said data latch circuit is at a logical one level if said output of said timing control circuit is at a logical one level and said data latch enable line is at a logical one level, and said output of said data latch circuit is at a logical one level if said output of said timing control circuit is at a logical one level and said output of said address lock circuit is at a logical zero level.

Claim 3

The timing control circuit of claim 1 wherein said timing control circuit comprises: a first inverter having an input and an output wherein said input of said first inverter is connected to said row address strobe line: a first NOR circuit having a first input, a second input, a third input, and an output and wherein said first input of said first NOR circuit is connected to said column address strobe line, said second input of said first NOR circuit is connected to said output of said first inverter, and said output of said first NOR circuit is said timing control circuit output; a second inverter having an input and an output wherein said input of second inverter is connected to said column address strobe line; a second NOR circuit having a first input, a second input, and an output wherein said first input of said second NOR circuit is connected to said inverse read line and said second input of said second NOR circuit is connected to said output of said second inverter; and a third NOR circuit having a first input, a second input, and an output wherein said first input of said third NOR circuit is connected to said output of said first NOR circuit, said second input of said third NOR circuit is connected to said output of said second NOR circuit, and said output of said third NOR circuit is connected to said third input of said first NOR circuit.

Claim 4

The timing control circuit of claim 1 wherein said address lock circuit comprises: a fourth NOR circuit having a first input, a second input and an output wherein said first input of said fourth NOR circuit is connected to said address lock enable line; a third inverter having an input and an output wherein said output of said third inverter is connected to said second input of said fourth NOR circuit; a first NAND circuit having a first input, a second input, and an output wherein said first input of said first NAND circuit is connected to said output of said fourth NOR circuit and said second input of said first NAND circuit is connected to said output of said timing control circuit; a fourth inverter having an input and an output wherein said input of said fourth inverter is connected to said column address strobe line; a fifth inverter having an input and an output wherein said input of said fifth inverter is connected to said output of said fourth inverter; a sixth inverter having an input and an output wherein said input of said sixth inverter is connected to said output of said fifth inverter; and a second NAND circuit having a first input, a second input, and an output wherein said first input of said second NAND circuit is connected to said output of said sixth inverter, said second input of said second NAND circuit is connected to said output of said first NAND circuit, and said output of said second NAND circuit is said output of said address lock circuit.

Claim 5

The timing control circuit of claim 1 wherein said data latch circuit comprises: a third NAND circuit having a first input, a second input, and an output wherein said first input of said third NAND circuit is connected to said output of said address lock circuit and said second input of said third NAND circuit is connected to said data latch enable line; a fourth NAND circuit having a first input, a second input, and an output wherein said first input of said fourth NAND circuit is connected to said output of said timing control circuit and said second input of said fourth NAND circuit is connected to said output of said third NAND circuit; and a seventh inverter having an input and an output wherein said input of said seventh inverter is connected to said output of said fourth NAND circuit and said output of said seventh inverter is said output of said data latch circuit.

Claim 6

A memory array control circuit, comprising: a row address strobe line; a column address strobe line; an inverse read line; a data latch enable line; an address lock enable line; a timing control circuit having a first input, a second input, a third input and an output wherein said first input of said timing control circuit is connected to said column address line, said second input of said timing control circuit is connected to said row address strobe line, said third input of said timing control circuit is connected to said inverse read line, said output of said timing control circuit is at a logical zero level when said row address strobe line is at a logical zero level or said column address strobe line is at a logical one level, and said output of said timing control circuit is at a logical one level when said row address strobe line is at a logical one level, said inverse read line is at a logical zero level, and said column address strobe line has switched from a logical one level to a logical zero level; an address lock circuit having a first input, a second input, and an output wherein said first input of said address lock circuit is connected to said column address strobe line, said second input of said address lock circuit is connected to said address lock enable line, said output of said address lock circuit is at a logical one level if said column address strobe line is at a logical one level, said output of said address lock circuit is at a logical one level if said address lock enable line is at a logical one level and said output of said timing control circuit is at a logical one level; a data latch circuit having a first input, a second input, and an output wherein said first input is connected to said data latch enable line, said second input is connected to said output of said timing control circuit and to said output of said address lock circuit, said output of said data latch circuit is at a logical one level if said output of said timing control circuit is at a logical one level and said data latch enable line is at a logical one level, and said output of said data latch circuit is at a logical one level if said output of said timing control circuit is at a logical one level and said output of said address lock circuit is at a logical zero level; a data circuit having a data line input, an inverse data line input, a data line enable output, and an address line enable output wherein said data circuit data line enable output is connected to said data latch circuit data line enable input and said data circuit address line enable output is connected to said address lock latch circuit address lock enable line input; an address input buffer having an address lock input and a number of address inputs wherein said address input buffer address lock input is connected to said address lock circuit output and said address inputs are connected to address signals; a data output buffer having a data latch input and a number of data outputs wherein said data output buffer data latch input is connected to said data latch circuit output, wherein: the address signals being prevented from entering said address input buffer when said address input buffer address lock input is at a logical one level; and the contents of said data output buffer being retained in said data output buffer when said data output buffer data latch input is at a logical one level.

Claim 7

A memory array control circuit, comprising: a row address strobe line; a column address strobe line; an inverse read line; a data latch enable line; an address lock enable line; a timing control circuit having a first input, a second input, a third input and an output wherein said first input of said timing control circuit is connected to said column address line, said second input of said timing control circuit is connected to said row address strobe line, said third input of said timing control circuit is connected to said inverse read line, said output of said timing control circuit is at a logical zero level when said row address strobe line is at a logical zero level or said column address strobe line is at a logical one level, and said output of said timing control circuit is at a logical one level when said row address strobe line is at a logical one level, said inverse read line is at a logical zero level, and said column address strobe line has switched from a logical one level to a logical zero level; an address lock circuit having a first input, a second input, and an output wherein said first input of said address lock circuit is connected to said column address strobe line, said second input of said address lock circuit is connected to said address lock enable line, said output of said address lock circuit is at a logical one level if said column address strobe line is at a logical one level, said output of said address lock circuit is at a logical one level if said address lock enable line is at a logical one level and said output of said timing control circuit is at a logical one level; a data latch circuit having a first input, a second input, and an output wherein said first input is connected to said data latch enable line, said second input is connected to said output of said timing control circuit and to said output of said address lock circuit, said output of said data latch circuit is at a logical one level if said output of said timing control circuit is at a logical one level and said data latch enable line is at a logical one level, and said output of said data latch circuit is at a logical one level if said output of said timing control circuit is at a logical one level and said output of said address lock circuit is at a logical zero level; a data circuit having a data line input, an inverse data line input, a data line enable output, and an address line enable output wherein said data circuit data line enable output is connected to said data latch circuit data line enable input and said data circuit address line enable output is connected to said address lock latch circuit address lock enable line input; an address input buffer having an address lock input and a number of address inputs wherein said address input buffer address lock input is connected to said address lock circuit output and said address inputs are connected to address signals; a data output buffer having a data latch input and a number of data outputs wherein said data output buffer data latch input is connected to said data latch circuit output, wherein: the address signals being prevented from entering said address input buffer when said address input buffer address lock input is at a logical one level; and the contents of said data output buffer being retained in said data output buffer when said data output buffer data latch input is at a logical one level.

Claim 8

The memory array control circuit of claim 5 wherein said timing control circuit comprises: a first inverter having an input and an output wherein said input of said first inverter is connected to said row address strobe line: a first NOR circuit having a first input, a second input, a third input, and an output and wherein said first input of said first NOR circuit is connected to said column address strobe line, said second input of said first NOR circuit is connected to said output of said first inverter, and said output of said first NOR circuit is said timing control circuit output; a second inverter having an input and an output wherein said input of second inverter is connected to said column address strobe line; a second NOR circuit having a first input, a second input, and an output wherein said first input of said second NOR circuit is connected to said inverse read line and said second input of said second NOR circuit is connected to said output of said second inverter; and a third NOR circuit having a first input, a second input, and an output wherein said first input of said third NOR circuit is connected to said output of said first NOR circuit, said second input of said third NOR circuit is connected to said output of said second NOR circuit, and said output of said third NOR circuit is connected to said third input of said first NOR circuit.

Claim 9

The memory array control circuit of claim 5 wherein said address lock circuit comprises: a fourth NOR circuit having a first input, a second input and an output wherein said first input of said fourth NOR circuit is connected to said address lock enable line; a third inverter having an input and an output wherein said output of said third inverter is connected to said second input of said fourth NOR circuit; a first NAND circuit having a first input, a second input, and an output wherein said first input of said first NAND circuit is connected to said output of said fourth NOR circuit and said second input of said first NAND circuit is connected to said output of said timing control circuit; a fourth inverter having an input and an output wherein said input of said fourth inverter is connected to said column address strobe line; a fifth inverter having an input and an output wherein said input of said fifth inverter is connected to said output of said fourth inverter; a sixth inverter having an input and an output wherein said input of said sixth inverter is connected to said output of said fifth inverter; and a second NAND circuit having a first input, a second input, and an output wherein said first input of said second NAND circuit is connected to said output of said sixth inverter, said second input of said second NAND circuit is connected to said output of said first NAND circuit, and said output of said second NAND circuit is said output of said address lock circuit.

Claim 10

The memory array control circuit of claim 5 wherein said data latch circuit comprises: a third NAND circuit having a first input, a second input, and an output wherein said first input of said third NAND circuit is connected to said output of said address lock circuit and said second input of said third NAND circuit is connected to said data latch enable line; a fourth NAND circuit having a first input, a second input, and an output wherein said first input of said fourth NAND circuit is connected to said output of said timing control circuit and said second input of said fourth NAND circuit is connected to said output of said third NAND circuit; and a seventh inverter having an input and an output wherein said input of said seventh inverter is connected to said output of said fourth NAND circuit and said output of said seventh inverter is said output of said data latch circuit.